AD679JNZ Ver la hoja de datos (PDF) - Analog Devices
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AD679JNZ Datasheet PDF : 16 Pages
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AD679
DIP Package
PIN CONFIGURATIONS
JLCC Package
EOCEN 1
OE 2
SC 3
CS 4
28 VDD
27 EOC
26 DB7
25 DB6
VEE 5
24 DB5
AIN
AGND
REFOUT
6
23 DB4
AD679
7 TOP VIEW 22 DB3
8 (Not to Scale) 21 DB2
REFIN 9
20 DB1
BIPOFF 10
19 DB0
VCC 11
DGND 12
18 DGND
17 DGND
SYNC 13
DGND 14
16 DGND
15 HBE
6 5 4 3 2 1 44 43 42 41 40
NC 7
VEE 8
NC 9
AIN 10
AGND 11
REFOUT 12
NC 13
REFIN 14
BIPOFF 15
NC 16
VCC 17
PIN 1
IDENTIFIER
AD679
TOP VIEW
(Not to Scale)
39 DB6
38 NC
37 DB5
36 DB4
35 DB3
34 DB2
33 DB1
32 NC
31 DB0
30 NC
29 NC
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
28-Lead 44-Lead
DIP
JLCC
Mnemonic Pin No. Pin No.
Type Name and Function
AGND
7
AIN
6
BIPOFF 10
CS
4
DGND 12, 14
DB7–DB0 26–19
EOC
27
EOCEN 1
HBE
15
OE
2
with
REFIN
9
REFOUT
8
SC
3
SYNC
13
VCC
11
VEE
5
VDD
28
—
16
—
17–18
11
P
10
AI
15
AI
6
DI
23
P
40, 39, 37, 36, DO
35, 34, 33, 31
42
DO
1
DI
25
DI
3
DI
14
AI
12
AO
5
DI
21
DI
17
P
8
P
43
P
U
2, 4, 7, 9, 13, U
16, 18, 19, 20,
22, 24, 26, 27,
28, 29, 30, 32,
38, 41, 44
Analog Ground. This is the ground return for AIN only.
Analog Signal Input.
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight
binary output coding. Connect to REFOUT for Ϯ5 V input bipolar mode and
twos complement binary output coding.
Chip Select. Active LOW.
Digital Ground.
Data Bits. These pins provide all 14 bits in two bytes (8 + 6 bits). Active HIGH.
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH
when the conversion finishes. In asynchronous mode, EOC is an open-drain
output and requires an external 3 kΩ pull-up resistor. See EOCEN and SYNC
pins for information on EOC gating.
End-of-Convert Enable. Enables EOC pin. Active LOW.
High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte (corresponding to the most recently read high byte).
Output Enable. A down-going transition on OE enables DB7 to DB0. Gated
CS. Active LOW.
Reference Input. 5 V input gives 10 V full-scale range.
5 V Reference Output. Tied to REFIN for normal operation.
Start Convert. Active LOW. See SYNC pin for gating.
SYNC Control. If tied to VDD (synchronous mode), SC and EOCEN are gated
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are indepen-
dent of CS, and EOC is an open-drain output. EOC requires an external 3 kΩ
pull-up resistor in asynchronous mode.
12 V Analog Power.
–12 V Analog Power.
5 V Digital Power.
Tie to DGND.
These pins are unused and should be connected to DGND or VDD.
Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers. P = Power. U = Unused.
–6–
REV. D
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