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AD571
(Rev.:RevA)

10-Bit A/D Converter

Analog Devices 

AD571

Figure 13. Sample-Hold Interface to the AD571

INTERFACING THE AD571 TO A MICROPROCESSOR

The AD571 can easily be arranged to be driven from standard

microprocessor control lines and to present data to any standard

microprocessor bus (4-, 8-, 12- or 16-bit) with a minimum of

additional control components. The configuration shown in

Figure 14 is designed to operate with an 8-bit bus and standard

8080 control signals.

the new data and the control lines will return to the standby

state. The 100 pF capacitor slows down the DR line enough to

be used as a latch signal for data outputs. The new data will

remain active until a new conversion is commanded. The self-

pulsing nature of this circuit guarantees a sufficient convert

pulse width.

This new data can now be presented to the data bus by en-

abling the three-state buffers when desired. A data word

(8-bit or 2-bit) is loaded onto the bus when its decoded ad-

dress goes low and the RD line goes low. This arrangement

presents data to the bus “left-justified,” with the highest bits in

the 8-bit word; a “right-justified” data arrangement can be set

up by a simple re-wiring. Polling the converter to determine if

conversion is complete can be done by addressing the gate

which buffers the DR line, as shown. In this configuration, there

is no need for additional buffer register storage: the data can be

held indefinitely in the AD571, since the B & C line is continu-

ally held low.

BUS INTERFACING WITH A PERIPHERAL INTERFACE

CIRCUIT

An improved technique for interfacing to a µP bus involves the

use of special peripheral interfacing circuits (or I/O devices),

such as the MC6821 Peripheral Interface Adapter (PIA). Shown

in Figure 15 is a straightforward application of a PIA to multi-

plex up to 8 AD571 circuits. The AD571 has 3-state outputs,

Figure 14. Interfacing AD571 to an 8-Bit Bus

(8080 Control Structure)

The input control circuitry shown is required to ensure that the

AD571 receives a sufficiently long B & C input pulse. When the

converter is ready to start a new conversion, the B & C line is

low, and DR is low. To command a conversion, the start ad-

dress decode line goes low, followed by WR. The B & C line

will now go high, followed about 1.5 µs later by DR. This resets

the external flip-flop and brings B & C back to low, which ini-

tiates the conversion cycle. At the end of the conversion cycle,

the DR line goes low, the data outputs will become active with

Figure 15. Multiplexing 8 AD571s Using Single PIA for

µP Interface. No Other Logic Required (6800 Control

Structure)

hence the data bit outputs can be paralleled, provided that only

one converter at a time is permitted to be the active state. The

DATA READY output of the AD571 is an open collector with

resistor pull-up, thus several DR lines can be wire-ored to

allow indication of the status of the selected device. One of the

8-bit ports of the PIA is combined with 2 bits from the other

port and programmed as a 10-bit input port. The remaining 6

bits of the second port are programmed as outputs and along

REV. A

–7–

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