AD571(RevA) Ver la hoja de datos (PDF) - Analog Devices
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AD571 Datasheet PDF : 8 Pages
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AD571
CONTROL AND TIMING OF THE AD571
There are several important timing and control features on the
AD571 which must be understood precisely to allow optimal
interfacing to microprocessor or other types of control systems.
All of these features are shown in the timing diagram in Figure
10.
The normal standby situation is shown at the left end of the
drawing. The BLANK and CONVERT (B & C) line is held
high, the output lines will be “open”, and the DATA READY
(DR) line will be high. This mode is the lowest power state of
the device (typically 150 mW). When the (B & C ) line is
brought low, the conversion cycle is initiated; but the DR and
data lines do not change state. When the conversion cycle is
complete, the DR line goes low, and within 500 ns, the data
lines become active with the new data.
About 1.5 µs after the B & C line is again brought high, the DR
line will go high and the data lines will go open. When the
B & C line is again brought low, a new conversion will begin.
The minimum pulse width for the B & C line to blank previous
data and start a new conversion is 2 µs. If the B & C line is
brought high during a conversion, the conversion will stop, and
the DR and data lines will not change. If a 2 µs or longer pulse
is applied to the B & C line during a conversion, the converter
will clear and start a new conversion cycle.
BLANK and CONVERT line is driven low and at the end of
conversion, which is indicated by DATA READY going low, the
conversion result will be present at the outputs. When this data
has been read from the 10-bit bus, BLANK and CONVERT is
restored to the blank mode to clear the data bus for other con-
verters. When several AD571s are multiplexed in sequence, a
new conversion may be started in one AD571 while data is
being read from another. As long as the data is read and the first
AD571 is cleared within 15 µs after the start of conversion of the
second AD571, no data overlap will occur.
Figure 11. Convert Pulse Mode
Figure 12. Multiplex Mode
Figure 10. AD571 Timing and Control Sequences
CONTROL MODES WITH BLANK AND CONVERT
The timing sequence of the AD571 discussed above allows the
device to be easily operated in a variety of systems with differing
control modes. The two most common control modes, the Con-
vert Pulse Mode and the Multiplex Mode, are illustrated here.
Convert Pulse Mode–In this mode, data is present at the output
of the converter at all times except when conversion is taking
place. Figure 11 illustrates the timing of this mode. The BLANK
and CONVERT line is normally low and conversions are trig-
gered by a positive pulse. A typical application for this timing
mode is shown in Figure 14, in which µP bus interfacing is
easily accomplished with three-state buffers.
Multiplex Mode—In this mode the outputs are blanked except
when the device is selected for conversion and readout; this tim-
ing is shown in Figure 12. A typical AD571 multiplexing appli-
cation is shown in Figure 15.
This operating mode allows multiple AD571 devices to drive
common data lines. All BLANK and CONVERT lines are held
high to keep the outputs blanked. A single AD571 is selected, its
SAMPLE-HOLD AMPLIFIER CONNECTION TO THE
AD571
Many situations in high-speed acquisition systems or digitizing
of rapidly changing signals require a sample-hold amplifier
(SHA) in front of the A-D converter. The SHA can acquire and
hold a signal faster than the converter can perform a conversion.
A SHA can also be used to accurately define the exact point in
time at which the signal is sampled. For the AD571, a SHA can
also serve as a high input impedance buffer.
Figure 13 shows the AD571 connected to the AD582 mono-
lithic SHA for high speed signal acquisition. In this configura-
tion, the AD582 will acquire a 10 volt signal in less than 10 µs
with a droop rate less than 100 µV/ms. The control signals are
arranged so that when the control line goes low, the AD582 is put
into the “hold” mode, and the AD571 will begin its conversion
cycle. (The AD582 settles to final value well in advance of the
first comparator decision inside the AD571). The DATA
READY line is fed back to the other side of the differential
input control gate so that the AD582 cannot come out of the
“hold” mode during the conversion cycle. At the end of the con-
version cycle, the DATA READY line goes low, automatically
placing the AD582 back into the sample mode. This feature al-
lows simple control of both the SHA and the A-D converter
with a single line. Observe carefully the ground, supply, and by-
pass capacitor connections between the two devices. This will
minimizes ground noise and interference during the conversion
cycle to give the most accurate measurements.
–6–
REV. A
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