AD5624R(RevA) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5624R Datasheet PDF : 28 Pages
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AD5624R/AD5644R/AD5664R
AD5624R-3/AD5644R-3/AD5664R-3
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Min
STATIC PERFORMANCE2
AD5664R
Resolution
16
Relative Accuracy
Differential Nonlinearity
AD5644R
Resolution
14
Relative Accuracy
Differential Nonlinearity
AD5624R
Resolution
12
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference TC3
Output Impedance
0
0
1.247
B Grade1
Typ
Max
±8
±16
±1
±2
±4
±0.5
±0.5
2
±1
−0.1
±2
±2.5
−100
10
10
5
25
20
10
2
10
0.5
30
4
170
26
±5
±10
7.5
±1
±0.25
10
±10
±1
±1.5
VDD
200
VDD
1.253
±15
Unit
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
μV/°C
ppm
dB
μV
μV/mA
μV
μV
μV/mA
μV
V
nF
nF
Ω
mA
μs
μA
V
kΩ
V
ppm/°C
ppm/°C
kΩ
Conditions/Comments
Guaranteed monotonic by design
Guaranteed monotonic by design
Guaranteed monotonic by design
All zeroes loaded to DAC register
All ones loaded to DAC register
Of FSR/°C
DAC code = midscale; VDD = 3 V ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
RL = ∞
RL = 2 kΩ
VDD = 3 V
Coming out of power-down mode; VDD = 3 V
VREF = VDD = 3.6 V
At ambient
MSOP package models
LFCSP package models
Rev. A | Page 5 of 28
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