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AD5533ABC-1_

32-Channel, 14-Bit DAC with Precision Infinite Sample-and-Hold Mode

Analog Devices 

PARALLEL INTERFACE TIMING DIAGRAM

CS

WR

A4–A0, CAL,

OFFS SEL

Figure 1. Parallel Write (ISHA Mode Only)

AD5532B

200␮A

IOL

TO

OUTPUT

PIN

CL

50pF

200␮A

IOH

1.6V

Figure 2. Load Circuit for DOUT Timing Specifications

SERIAL INTERFACE TIMING DIAGRAMS

SCLK

SYNC

DIN

t1

1

2

3

4

5

6

7

8

9

t3

t2

t4

t5

t6

MSB

Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)

10

LSB

SCLK

SYNC

DIN

t1

1

2

3

4

5

21

22

23

24

1

t3

t2

t4

MSB

t5

t6

Figure 4. 24-Bit Write (DAC Mode)

t11

LSB

SCLK 10

SYNC

DOUT

t7

t1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

t12

t2

t10

t4

t8

t9

MSB

LSB

Figure 5. 14-Bit Read (Both Readback Modes)

REV. A

–5–

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