AD5530_02 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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AD5530_02 Datasheet PDF : 16 Pages
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AD5530/AD5531
STANDALONE TIMING CHARACTERISTICS1, 2 (VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V;
RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
7
t1
140
t2
60
t3
60
t4
50
t5
40
t6
50
t7
40
t8
15
t9
5
t10
50
t11
5
t12
50
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Frequency
SCLK Cycle Time
SCLK Low Time
SCLK High Time
SYNC to SCLK Falling Edge Setup Time
SCLK Falling Edge to SYNC Rising Edge
Min SYNC High Time
Data Setup Time
Data Hold Time
SYNC High to LDAC Low
LDAC Pulsewidth
LDAC High to SYNC Low
CLR Pulsewidth
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns
(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
Specifications subject to change without notice.
SCLK
SYNC
SDIN
LDAC*
t1
t4
t6
MSB
DB15
DB14
t7 t8
DB11
t3
t2
t5
LSB
DB0
t9
t11
t10
t12
CLR
*LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED
Figure 1. Timing Diagram for Standalone Mode
–4–
REV. 0
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