AD5453 Ver la hoja de datos (PDF) - Analog Devices
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AD5453 Datasheet PDF : 28 Pages
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Data Sheet
AD5450/AD5451/AD5452/AD5453
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RFB 1
VREF 2
VDD 3
SYNC 4
AD5450/
AD5451/
AD5452/
AD5453
8 IOUT1
7 GND
6 SCLK
5 SDIN
Figure 3. 8-Lead TSOT Pin Configuration
IOUT1 1
GND 2
SCLK 3
SDIN 4
AD5452/
AD5453
8 RFB
7 VREF
6 VDD
5 SYNC
Figure 4. 8-Lead MSOP Pin Configuration
IOUT1 1
GND 2
SCLK 3
SDIN 4
AD5453
TOP VIEW
(Not to Scale)
8 RFB
7 VREF
6 VDD
5 SYNC
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
Figure 5. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No1
TSOT MSOP LFCSP Mnemonic
1
8
8
RFB
2
7
7
VREF
3
6
6
VDD
4
5
5
SYNC
5
4
4
SDIN
6
3
3
SCLK
7
2
8
1
N/A N/A
2
1
EPAD
GND
IOUT1
EPAD
Description
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
DAC Reference Voltage Input.
Positive Power Supply Input. These devices can operate from a supply of 2.5 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge of
the serial clock input. Alternatively, by means of the serial control bits, the device can be configured
such that data is clocked into the shift register upon the rising edge of SCLK.
Ground Pin.
DAC Current Output.
Exposed pad must be connected to ground.
1 N/A = not applicable.
Rev. H | Page 7 of 28
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