AD5453 Ver la hoja de datos (PDF) - Analog Devices
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AD5453 Datasheet PDF : 28 Pages
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Data Sheet
AD5450/AD5451/AD5452/AD5453
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
Update Rate
VDD = 2.5 V to 5.5 V
50
20
8
8
8
5
4.5
5
30
2.7
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Description
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
SCLK
SYNC
DIN
t8
t4
DB15
t6
t5
t1
t2
t3
t7
DB0
Figure 2. Timing Diagram
Rev. H | Page 5 of 28
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