AD5453YUJ(RevPrD) Ver la hoja de datos (PDF) - Analog Devices

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componentes Descripción

Fabricante

AD5453YUJ
(Rev.:RevPrD)

8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface

Analog Devices 

MSOP

1

2

3

TSOT

8

7

6

4

5

5

4

6

3

7

2

8

1

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

PIN FUNCTION DESCRIPTION

Mnemonic Function

IOUT1

GND

SCLK

SDIN

SYNC

VDD

VREF

RFB

DAC Current Output.

Ground Pin.

Serial Clock Input. By default, data is clocked into the input shift register on the

falling edge of the serial clock input. Alternatively, by means of the serial control

bits, the device may be configured such that data is clocked into the shift register on

the rising edge of SCLK.

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of

the serial clock input. By default, on power up, data is clocked into the shift register

on the falling edge of SCLK. The control bits allow the user to change the active

edge to rising edge.

Active Low Control Input. This is the frame synchronization signal for the input

data. Data is loaded to the shift register on the active edge of the

following clocks.

Positive power supply input. These parts can operate from a supply of +2.5 V to

+5.5 V.

DAC reference voltage input pin.

DAC feedback resistor pin. Establish voltage output for the DAC by connecting to

external amplifier output.

TSOT (UJ-8)

PIN CONFIGURATION

MSOP (RM-8)

RFB 1

VREF 2

VDD 3

SYNC 4

AD5450/

AD5451/

AD5452/

AD5453

(Not to Scale)

8 IOUT1

7 GND

6 SCLK

5 SDIN

IOUT1 1

8 RFB

GND 2

AD5452/

AD5453

7 VREF

SCLK 3 (Not to Scale) 6 VDD

SDIN 4

5 SYNC

REV. PrD

–5–

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