AD5453YUJ(RevPrD) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5453YUJ
(Rev.:RevPrD)
(Rev.:RevPrD)
Analog Devices
AD5453YUJ Datasheet PDF : 16 Pages
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PRELIMINARY TECHNICAL DATA
AD5450/AD5451/AD5452/AD5453
(VDD = 2.5 V to 5.5 V, VREF = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with
OP1177, AC performance with AD9631 unless otherwise noted.)
Parameter
Min Typ
Total Harmonic Distortion
-80
Digital THD, Clock = 1MHz
50kHz fOUT
75
Output Noise Spectral Density
25
SFDR performance (Wideband)
Update = 1MHz
50kHz Fout
78
20kHz Fout
78
SFDR performance (NarrowBand)
50kHz Fout
87
20kHz Fout
87
Intermodulation Distortion
78
Max
POWER REQUIREMENTS
Power Supply Range
2.5
IDD
Power Supply Sensitivity2
5.5
1
0.001
NOTES
1Temperature range is as follows: Y Version: –40°C to +125°C.
2Guaranteed by design and characterisation, not subject to production test.
Specifications subject to change without notice.
Units
dB
Conditions
VREF = 3.5 V pk-pk, All 1s loaded, f = 1kHz
dB
nV/√Hz
@ 1kHz
Update = 1MHz, VREF = 3.5V
dB
dB
Update = 1MHz, VREF = 3.5V
dB
dB
dB
f1 = 20kHz, f2 = 25kHz, Update=1MHz,
VREF=3.5V
V
µA
%/%
Logic Inputs = 0 V or VDD
∆VDD = ±5%
TIMING CHARACTERISTICS1
(VREF = +5 V, IOUT2 = O V. All specifications TMIN to TMAX unless otherwise noted.)
Parameter VDD = 4.5 V to 5.5 V VDD = 2.5 V to 5.5 V Units
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
50
MHz max Max Clock frequency
20
ns min SCLK Cycle time
8
ns min SCLK High Time
8
ns min SCLK Low Time
8
ns min
SYNC falling edge to SCLK active edge setup time
5
ns min Data Setup Time
4.5
ns min Data Hold Time
5
ns min
SYNC rising edge to SCLK active edge
30
ns min
Minimum SYNC high time
NOTES
1See Figures 1. Temperature range is as follows: Y Version: –40°C to +125°C. Guaranteed by design and characterisation, not subject to
production test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
SCLK
SYNC
DIN
t8
t4
DB15
t6
t5
t1
t2
t3
t7
DB0
REV. PrD
Figure 1. Timing Diagram.
–3–
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