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AD5453YUJ
(Rev.:RevPrD)

8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface

Analog Devices 

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453–SPECIFICATIONS1

(VDD = 2.5 V to 5.5 V, VREF = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with

OP1177, AC performance with AD9631 unless otherwise noted.)

Parameter

Min Typ Max

Units

Conditions

STATIC PERFORMANCE

AD5450

Resolution

Relative Accuracy

Differential Nonlinearity

AD5451

Resolution

Relative Accuracy

Differential Nonlinearity

AD5452

Resolution

Relative Accuracy

Differential Nonlinearity

AD5453

Resolution

Relative Accuracy

Differential Nonlinearity

Total Unadjusted Error

Gain Error

Gain Error Temp Coefficient2

Output Leakage Current

Output Voltage Compliance Range

±5

1.23

8

±0.25

±½

10

±0.25

±½

12

±0.5

±½

14

±2

±1

±2.44

±1.22

±10

±50

Bits

LSB

LSB

Guaranteed Monotonic

Bits

LSB

LSB

Guaranteed Monotonic

Bits

LSB

LSB

Guaranteed Monotonic

Bits

LSB

LSB

Guaranteed Monotonic

mV

mV

ppm FSR/°C

nA

Data = 0000H, TA = 25°C, IOUT1

nA

Data = 0000H, IOUT1

V

REFERENCE INPUT2

Reference Input Range

VREF Input Resistance

±10

V

8

9.3

12

kΩ

DIGITAL INPUTS2

Input High Voltage, VIH

2.0

1.7

Input Low Voltage, VIL

Input Leakage Current, IIL

Input Capacitance

V

V

0.8

V

0.7

V

1

µA

10

pF

Input resistance TC = -50ppm/°C

VDD = 3.6 V to 5 V

VDD = 2.5 V to 3.6 V

VDD = 2.7 V to 5.5 V

VDD = 2.5 V to 2.7 V

DYNAMIC PERFORMANCE2

Reference Multiplying BW

Output Voltage Settling Time

AD5450

AD5451

AD5452

AD5453

Digital Delay

10% to 90% Dettling Time

Digital to Analog Glitch Impulse

Multiplying Feedthrough Error

Output Capacitance

IOUT1

IOUT2

Digital Feedthrough

10

100

110

160

180

20

40

10

30

3

-75

5

10

10

5

0.1

MHz

ns

ns

ns

ns

ns

ns

nV-s

dB

pF

pF

pF

pF

nV-s

VREF = +/-3.5V, DAC loaded all 1s

VREF = 10V, RLOAD = 100Ω, CLOAD = 15pF

DAC latch alternately loaded with 0s and 1s.

Measured to +/-16mV of FS

Measured to +/-4mV of FS

Measured to +/-1mV of FS

Measured to +/-1mV of FS

Interface delay time

Rise and Fall time, VREF = 10V, RLOAD =

100Ω, CLOAD = 15pF

1 LSB change around Major Carry, VREF=0V

DAC latch loaded with all 0s.

Reference = 1MHz.

Reference = 10MHz.

DAC Latches Loaded with all 0s

DAC Latches Loaded with all 1s

DAC Latches Loaded with all 0s

DAC Latches Loaded with all 1s

Feedthrough to DAC output with CS high

and Alternate Loading of all 0s and all 1s.

–2–

REV. PrD

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