AD5453YUJ(RevPrD) Ver la hoja de datos (PDF) - Analog Devices

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AD5453YUJ
(Rev.:RevPrD)

8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface

Analog Devices 

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

GENERAL DESCRIPTION

DAC SECTION

The AD5450, AD5451, AD5452 and AD5453 are 8, 10,

12 and 14 bit current output DACs consisting of a

segmented (4-Bits) inverting R-2R ladder configuration.

The feedback resistor RFB has a value of R. The value of R

is typically 9.3kΩ (minimum 8kΩ and maximum 12kΩ).

If IOUT1 is kept at the same potential as GND, a constant

current flows in each ladder leg, regardless of digital input

code. Therefore, the input resistance presented at VREF is

always constant and nominally of value R. The DAC

output (IOUT) is code-dependent, producing various

resistances and capacitances. External amplifier choice

should take into account the variation in impedance

generated by the DAC on the amplifiers inverting input

node.

Access is provided to the VREF, RFB, and IOUT1 terminals

of the DAC, making the device extremely versatile and

allowing it to be configured in several different operating

modes, for example, to provide a unipolar output and in

four quadrant multiplication in bipolar mode. Note that a

matching switch is used in series with the internal RFB

feedback resistor. If users attempt to measure RFB, power

must be applied to VDD to achieve continuity.

SERIAL INTERFACE

The AD5450/AD5451/AD5452/AD5453 have an easy to

use 3-wire interface which is compatible with SPI/QSPI/

MicroWire and DSP interface standards. Data is written

to the device in 16 bit words. This 16-bit word consists of

2 control bits and either 8, 10 12, or 14 data bits as shown

in Figure 2. The AD5453 uses all 14 bits of DAC data.

The AD5452 uses twelve bits and ignores the two LSBs,

similarly the AD5451 uses ten bits and ignores the four

LSBs, while the AD5450 uses eight bits and ignores the

last six bits.

DAC Control Bits C1, C0

Control bits C1 and C0 the user to load and update the

new DAC code and to change the active clock edge. By

default the shift register clocks data in on the falling edge,

this can be changed via the control bits. In this case, the

DAC core is inoperative until the next data frame. A

power cycle resets this back to default condition.

On chip power on reset circuitry ensures the device

powers on with zeroscale loaded to the DAC register and

IOUT line.

TABLE III. DAC CONTROL BITS

C1 C0 Funtion Implemented

0 0 Load and Update(Power On Default)

0 1 Reserved

1 0 Reserved

1 1 Clock Data to shift register On Rising Edge

SYNC Function

SYNC is an edge-triggered input that acts as a frame

synchronization signal and chip enable. Data can only be

transferred into the device while SYNC is low. To start

the serial data transfer, SYNC should be taken low ob-

serving the minimum SYNC falling to SCLK falling

edge setup time, t4.

After the falling edge of the 16th SCLK pulse, bring

SYNC high to transfer data from the input shift register to

the DAC register.

DB15 (MSB)

DB0 (LSB)

C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X

CONTROL BITS

DATA BITS

Figure 2a. AD5450 8 bit Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X

CONTROL BITS

DATA BITS

Figure 2b. AD5451 10 bit Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X

CONTROL BITS

DATA BITS

REV. PrD

Figure 2c. AD5452 12 bit Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

C1 C0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CONTROL BITS

DATA BITS

Figure 2c. AD5453 14 bit Input Shift Register Contents

–11–

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