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AD53519

Dual Ultrafast Voltage Comparator

Analog Devices 

AD53519

PRELIMINARY TECHNICAL DATA

APPLICATIONS INFORMATION

The AD53519 comparators are very high speed devices.

Consequently, high speed design techniques must be

employed to achieve the best performance. The most critical

aspect of any AD53519 design is the use of low impedance

ground plane. A ground plane, as part of a multilayer board,

is recommended for proper high speed performance. Using a

continuous conductive plane over the surface of the circuit

board can create this, only allowing breaks in the plane for

necessary current paths. The ground plane provides a low

inductance ground, eliminating any potential differences at

different ground points throughout the circuit board caused

by “ground bounce”. A proper ground plane also minimizes

the effects of stray capacitance on the circuit board.

It is also important to provide bypass capacitors for the power

supply in a high speed application. A 1µF electrolytic bypass

capacitor should be placed within 0.5 inches of each power

supply pin to ground. These capacitors will reduce any

potential voltage ripples from the power supply. In addition,

a 10nF ceramic capacitor should be placed as close as

possible from the power supply pins on the AD53519 to

ground. These capacitors act as a charge reservoir for the

device during high frequency switching.

The LATCH ENABLE input is active LOW (latched). If the

latching function is not used, the LATCH ENABLE input

should be grounded (ground is an ECL logic HIGH). The

complimentary input, /LATCH ENABLE, should be tied to

–2.0 V to disable the latching function.

Occasionally, one of the two comparator stages within the

AD53519 will not be used. The inputs of the unused

comparator should not be allowed to “float”. The high

internal gain may cause the output to oscillate (possibly

affecting the other comparator which is being used) unless the

output is forced into a fixed state. This is easily

accomplished by insuring that the two inputs are at least one

diode drop apart, while also appropriately connecting the

LATCH ENABLE and /LATCH ENABLE inputs as

described above.

The best performance will be achieved with the use of proper

ECL terminations. The open-emitter outputs of the AD53519

are designed to be terminated through 50Ω resistors to –2.0

V, or any other equivalent ECL termination. If a –2.0 V

supply is not available, an 82Ω resistor to ground and a 130Ω

resistor to –5.2 V provides a suitable equivalent. If high

speed ECL signals must be routed more than a centimeter,

microstrip or stripline techniques may be required to insure

proper transition times and prevent output ringing.

Clock Timing Recovery

Comparators are often used in digital systems to recover clock

timing signals. High-speed square waves transmitted over a

distance, even tens of centimeters, can become distorted due to

stray capacitance and inductance. Poor layout or improper

termination can also cause reflections on the transmission line,

further distorting the signal waveform. A high-speed

comparator can be used to recover the distorted waveform while

maintaining a minimum of delay.

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator or amplifier, proper design

and layout techniques should be used to ensure optimal

performance from the AD53519. The performance limits of

high speed circuitry can easily be a result of stray capacitance,

improper ground impedance or other layout issues.

Minimizing resistance from source to the input is an important

consideration in maximizing the high speed operation of the

AD53519. Source resistance in combination with equivalent

input capacitance could cause a lagged response at the input,

thus delaying the output. The input capacitance of the

AD53519 in combination with stray capacitance from an input

pin to ground could result in several picofarads of equivalent

capacitance. A combination of 3 kΩ source resistance and 5 pF

of input capacitance yield a time constant of 15ns, which is

significantly slower than the sub 500 ps capability of the

AD53519. Source impedances should be significantly less than

100 Ω for best performance.

Sockets should be avoided due to stray capacitance and

inductance. If proper high speed techniques are used, the

AD53519 should be free from oscillation when the comparator

input signal passes through the switching threshold.

COMPARATOR PROPAGATION DELAY

DISPERSION

The AD53519 has been specifically designed to reduce

propagation delay dispersion over an input overdrive range of

100 mV to 1 V. Propagation delay dispersion is the change in

propagation delay which results from a change in the degree of

overdrive (how far the switching point is exceeded by the

input). The overall result is a higher degree of timing accuracy

since the AD53519 is far less sensitive to input variations than

most comparator designs.

Propagation delay dispersion is a specification, which is

important in critical timing application such as ATE, bench

instruments and nuclear instrumentation. Dispersion is defined

as the variation in propagation delay as the input overdrive

conditions are changed. For the AD53519 dispersion is

typically 50 ps as the overdrive is changed from 100 mV to 1 V.

This specification applies for both positive and negative

overdrive since the AD53519 has equal delays for positive and

negative going inputs.

The 50 ps propagation delay dispersion of the AD53519 offers

considerable improvement of the 100 ps dispersion of other

similar series comparators.

REV. Pr J July 22, 2002

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