AD5362 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5362 Datasheet PDF : 25 Pages
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Preliminary Technical Data
Parameter
POWER REQUIREMENTS
DVCC
VDD
VSS
Power Supply Sensitivity2
∆ Full Scale/∆ VDD
∆ Full Scale/∆ VSS
∆ Full Scale/∆ VCC
DICC
IDD
ISS
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature3
B Version 1 Unit
Test Conditions/Comments2
2.3/5.5
8/16.5
−4.5/−16.5
V min/max
V min/max
V min/max
−75
dB typ
−75
dB typ
−90
dB typ
2
mA max
VCC = 5.5 V, VIH = VCC, VIL = GND.
5
mA max
Outputs unloaded.
5
mA max
Outputs unloaded.
350
mW
130
°C max
TJ = TA + PTOTAL × θJ.
1 Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
3 Where θJ represents the package thermal impedance.
AD5362/AD5363
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 kΩ;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. AC Characteristics
Parameter
B Version
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
20
30
Slew Rate
1
Digital-to-Analog Glitch Energy
20
Glitch Impulse Peak Amplitude
10
Channel-to-Channel Isolation
100
DAC-to-DAC Crosstalk
40
10
Digital Crosstalk
0.1
Digital Feedthrough
1
Output Noise Spectral Density @ 10 kHz 250
1Guaranteed by design and characterization. Not production tested
Unit
Test Conditions/Comments
µs typ
µs max
V/µs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s.
VREF = 2 V p-p, 1 kHz.
Between DACs in the same group.
Between DACs from different groups.
Effect of input bus activity on DAC output under test.
VREF = 0 V.
Rev. PrF | Page 5 of 25
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