AD5360 Ver la hoja de datos (PDF) - Analog Devices

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AD5360

16-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC

Analog Devices 

Preliminary Technical Data

AD5360/AD5361

GENERAL DESCRIPTION

The AD5360/AD5361 contains 16, 16/14-bit DACs in a single,

56-lead, LFCSP or 52-lead LQFP package. It provides buffered

voltage outputs with a span 4 times the reference voltage. The

gain and offset of each DAC can be independently trimmed to

remove errors. For even greater flexibility, the device is divided

into two groups of 8 DACs, and the output range of each group

can be independently adjusted by an offset DAC.

The AD5360/AD5361 offers guaranteed operation over a wide

supply range with VSS from -4.5 V to -16.5 V and VDD from

+8 V to +16.5 V. The output amplifier headroom requirement is

1.4 V operating with a load current of 1 mA.

Table 1. High Channel Count Bipolar DACs

Model

Resolution Nominal Output

Span

AD5360BCPZ

AD5360BSTZ

AD5361BCPZ

AD5361BSTZ

AD5362BCPZ

AD5362BSTZ

AD5363BCPZ

AD5363BSTZ

AD5370BCPZ

AD5370BSTZ

AD5371BCPZ

AD5371BSTZ

AD5372BCPZ

AD5372BSTZ

AD5373BCPZ

AD5373BSTZ

16 Bits

16 Bits

14 Bits

14 Bits

16 Bits

16 Bits

14 Bits

14 Bits

16 Bits

16 Bits

14 Bits

14 Bits

16 Bits

16 Bits

14 Bits

14 Bits

4 × VREF (20 V)

4 × VREF (20 V)

4 × VREF (20 V)

4 × VREF (20 V)

4 × VREF (20 V)

4 × VREF (20 V)

4 × VREF (20 V)

4 × VREF (20 V)

4 × VREF (12 V)

4 × VREF (12 V)

4 × VREF (12 V)

4 × VREF (12 V)

4 × VREF (12 V)

4 × VREF (12 V)

4 × VREF (12 V)

4 × VREF (12 V)

Output

Channels

16

16

16

16

8

8

8

8

40

40

40

40

32

32

32

32

The AD5360/AD5361 has a high-speed 4-wire serial interface,

which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP

interface standards and can handle clock speeds of up to 50

MHz. All the outputs can be updated simultaneously by taking

the LDAC input low. Each channel has a programmable gain

and an offset adjust register.

Each DAC output is amplified and buffered on-chip with

respect to an external SIGGND input. The DAC outputs can

also be switched to SIGGND via the CLR pin.

Linearity Error

(LSB)

±4

±4

±1

±1

±4

±4

±1

±1

±4

±4

±2

±2

±4

±4

±2

±2

Package Description Package Option

56-Lead LFCSP

52-Lead LQFP

56-Lead LFCSP

52-Lead LQFP

56-Lead LFCSP

52-Lead LQFP

56-Lead LFCSP

52-Lead LQFP

64-Lead LFCSP

64-Lead LQFP

100-Ball CSPBGA

80-Lead LQFP

56-Lead LFCSP

64-Lead LQFP

56-Lead LFCSP

64-Lead LQFP

CP-56

ST-52

CP-56

ST-52

CP-56

ST-52

CP-56

ST-52

CP-64

ST-64

BC-100-2

ST-80

CP-56

ST-64

CP-56

ST-64

Rev. PrF | Page 3 of 25

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