AD5263BRUZ200 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD5263BRUZ200

Quad, 15 V, 256-Position, Digital Potentiometer with Pin-Selectable SPI/I2C

Analog Devices 

AD5263

Parameter

POWER SUPPLIES

Logic Supply8

Power Single-Supply Range

Power Dual-Supply Range

Logic Supply Current9

Positive Supply Current

Negative Supply Current

Power Dissipation10

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS6, 11

Bandwidth (3 dB)

Total Harmonic Distortion

VW Settling Time12

Resistor Noise Voltage

Symbol Conditions

Min

VL

VDD RANGE

VDD/SS RANGE

IL

IDD

ISS

PDISS

PSS

VSS = 0 V

VL = +5 V

VIH = +5 V or VIL = 0 V

VSS = –5 V

VIH = +5 V or VIL = 0 V, VDD = +5

V, VSS = –5 V

∆VDD = +5 V ± 10%

2.7

VL

±4.5

BW

THDW

tS

eN_WB

RAB = 20 kΩ/50 kΩ/200 kΩ

VA = 1 V rms, VB = 0 V, f = 1 kHz,

RAB = 20 kΩ

VA = 10 V, VBB = 0 V, ±1 LSB error

band

RWB = 10 kΩ, f = 1 kHz, RS = 0

Typ 1

Max

5.5

16.5

±7.5

25

60

1

1

0.6

0.002

0.01

300/150/35

0.05

2

9

Unit

V

V

V

μA

μA

μA

mW

%/%

kHz

%

μs

nV/√Hz

1 Typicals represent average readings at +25°C and VDD = +5 V, VSS = −5 V.

2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and

VSS = –5 V.

3 VAB = VDD, Wiper (VW) = no connect.

4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.

6 Guaranteed by design and not subject to production test.

7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.

8 VL is limited to VDD or 5.5 V, whichever is less.

9 Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.

10 PDISS is calculated from IDD × VDD. CMOS logic level inputs result in minimum power dissipation.

11 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V.

12 Settling time depends on value of VDD, RL, and CL.

Rev. A | Page 4 of 28

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