AD484M1644VTA Ver la hoja de datos (PDF) - Unspecified

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componentes Descripción

Fabricante

AD484M1644VTA

64Mb( 4Banks ) Synchronous DRAM

Unspecified 

Ascend Semiconductor Corporation 64Mb SDRAM

Pin Descriptions ( Simplified )

Pin

CLK

/CS

CKE

A0 ~ A11

BA0, BA1

/RAS

/CAS

/WE

Name

System Clock

Chip select

Clock Enable

Address

Bank Address

Pin Function

Master Clock Input(Active on the Positive rising edge)

Selects chip when active

Activates the CLK when “H” and deactivates when “L”.

CKE should be enabled at least one cycle prior to new

command. Disable input buffers for power down in standby.

Row address (A0 to A11) is determined by A0 to A11 level

at the bank active command cycle CLK rising edge.

CA(CA0 to CA7) is determined by A0 to A7 level at the

read or write command cycle CLK rising edge.

And this column address becomes burst access start

address. A10 defines the pre-charge mode. When A10 = High

at the pre-charge command cycle, all banks are pre-charged.

But when A10 = Low at the pre-charge command cycle,

only the bank that is selected by BA0/BA1 is pre-charged.

Selects which bank is to be active.

Row address strobe

Column address strobe

Write Enable

Latches Row Addresses on the positive rising edge of the

CLK with /RAS “L”. Enables row access & pre-charge.

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

LDQM/ UDQM

Data input/output Mask

DQM controls I/O buffers.

DQ0 ~ 15

VDD/VSS

VDDQ/VSSQ

NC

Data input/output

DQ pins have the same function as I/O pins on a conventional

DRAM.

Power supply/Ground

Power supply/Ground

No connection

VDD and VSS are power supply pins for internal circuits.

VDDQ and VSSQ are power supply pins for the output buffers.

This pin is recommended to be left No Connection on the

device.

Preliminary

5

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