AD5171 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5171 Datasheet PDF : 24 Pages
| |||
AD5171
TIMING CHARACTERISTICS: 5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 3 V to 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
INTERFACE TIMING CHARACTERISTICS (APPLY TO ALL PARTS2, 3)
SCL Clock Frequency
tBUF Bus Free Time Between Start and Stop
tHD;STA Hold Time (Repeated Start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for Stop Condition
OTP Program Time
Symbol Conditions
fSCL
t1
t2
After this period, the
first clock pulse is generated
t3
t4
t5
t6
t7
t8
t9
t10
t11
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design; not subject to production test.
3 All dynamic characteristics use VDD = 5 V.
Min Typ1 Max Unit
400 kHz
1.3
μs
0.6
μs
1.3
μs
0.6
50 μs
0.6
μs
0.9 μs
0.1
μs
0.3 μs
0.3 μs
0.6
μs
400
ms
t8
t9
t6
SCL
SDA
t2
t3
t8
t1
P
S
t4
t5
t7
t9
Figure 3. Interface Timing Diagram
t10
P
Rev. D | Page 5 of 24
Share Link: 