AD5111(Rev0) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5111
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5111 Datasheet PDF : 24 Pages
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Data Sheet
AD5111/AD5113/AD5115
INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
fCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
tEEPROM_PROGRAM1
tPOWER_UP2
Test Conditions/Comments Min Typ
VDD ≥ 2.7 V
VDD < 2.7 V
25
VDD ≥ 2.7 V
10
VDD < 2.7 V
20
VDD ≥ 2.7 V
10
VDD < 2.7 V
20
15
6
VDD ≥ 2.7 V
20
VDD < 2.7 V
40
15
VDD ≥ 2.7 V
12
VDD < 2.7 V
24
12
1
15
Max Unit
50 MHz
25 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
50 ms
50 µs
Description
Clock frequency
CS setup time
CLK low time
CLK high time
U/D setup time
U/D hold time
CS rise to CLK hold time
CS rising edge to next CLK ignored
U/D minimum pulse time
U/D rise to CLK falling edge
Minimum CS time
Memory program time
Power-on EEPROM restore time
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
2 Maximum time after VDD is equal to 2.3 V.
TIMING DIAGRAMS
t1
t2
t3
t6
t10
CS
CLK
U/D
t7
t4
t5
RWB
Figure 2. Increment/Decrement Mode Timing
t1
t8
t6
CS
t1
CS
t9
t6
CLK
U/D
Figure 4. Shutdown Mode Timing
CLK
U/D
tEEPROM_PROGRAM
EEPROM
DATA
NEW DATA
Figure 3. Storage Mode Timing
Rev. 0 | Page 9 of 24
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