AD5111(Rev0) Ver la hoja de datos (PDF) - Analog Devices

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AD5111
(Rev.:Rev0)

Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5111/AD5113/AD5115

VDD 1

A2

W3

B4

AD5111/

AD5113/

AD5115

TOP VIEW

(Not to Scale)

8 CS

7 U/D

6 CLK

5 GND

NOTES

1. THE EXPOSED PAD IS INTERNALLY

FLOATING.

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1

VDD

Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

2

A

Terminal A of RDAC. GND ≤ VA ≤ VDD.

3

W

Wiper Terminal of RDAC. GND ≤ VW ≤ VDD.

4

B

Terminal B of RDAC. GND ≤ VB ≤ VDD.

5

GND

Ground Pin, Logic Ground Reference.

6

CLK

Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined

by the state of the U/D pin. CLK is a negative edge trigger. Data can be transferred at rates up to 50 MHz.

7

U/D

Up/Down Selection Counter Control.

8

CS

Chip Select. Active Low.

EPAD

Exposed Pad. The exposed pad is internally floating.

Rev. 0 | Page 11 of 24

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