AD22157 Ver la hoja de datos (PDF) - Analog Devices
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AD22157 Datasheet PDF : 7 Pages
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AD22157
The mid point of these potentials is used as a reference for a
tor and watchdog timer.
zero crossing detector in the PWM. This system assures that a
phase jitter specification of +/- 2% for 1kHz signal (rising edge
to rising edge) can be met over all operational conditions.
The timing sequence is as follows:
i. The counter is reset upon receipt of a zero crossing event.
Tracker1 also makes an absolute measurement of peak to peak
ii. The leading edge of the pulse is output after a delay of 45uS.
signal. The digital result is a measure of field strength which
iii. Amplitude thresholds are decoded with direction and the
can be related directly to air gap or used for diagnostic purposes appropriate output pulse width is generated.
in the application. The digital result is combined with direction
information from Tracker 2 and used to program the output
iv. The counter is reset.
pulse width modulator (PWM).
v. If a zero crossing is not received before the counter overflows
The absolute peak to peak value of the Hall signal may vary due (745 uS), a STOP pulse is output.
to air gap settings and alter dynamically due to wheel run out. A
fixed resolution converter may fail to maintain acquisition of
the signal peaks using only single 1lsb steps. To compensate for
this, the resolution of the converters adapts to changes in the
signal that cannot be followed using 1lsb steps.
E HALL PLATE BIAS
The Hall cells are biased so that the temperature coefficient of
sensitivity of the AD22157 is of similar magnitude but opposite
polarity to rare earth magnetic materials i.e. SmCo = - 450ppm/
T C. or Alnico 5 -7 = -300 ppm/C. This results in good stability of
the PWM thresholds.
The purpose of resetting the trackers is to enable the offset cor-
rection circuitry to remain active when no zero crossing events
occur but when thermally induced drift may invalidate the offset
correction over extended periods of inactivity.
The sensor supply loop current is modulated in response to the
pulse input between two discrete current levels of approxi-
mately 7 mA and 14 mA. The lower current value being the qui-
escent or logic low state.
E OPERATIONAL MODES
On receipt of a power on reset or a stopped or no field condition
the sample hold circuits in each tracker channel reset to their
L maximum and minimum voltages. They then track inwards until
the Hall signal is acquired.
Tracker1(S/H_max) increments to the most positive Hall signal
peak, Tracker1(S/H_min) decrements to negative peaks.
O Four zero crossing events are required to ensure Hall signal
peak acquisition. No output edges are enabled during this time.
On the third zero crossing after the reset condition the acquire
mode of operation is disabled. The DAC signals are then coinci-
S dent with the peak values of the Hall signal. After the four zero
crossing delay, the converters enter dither mode. This mode of
operation keeps the DAC voltages at the peaks of the Hall signal
and maintains a valid zero crossing in the presence of run out
B and offset drift.
PWM AND OUTPUT STAGE
The pulse width modulator is the final stage of the signal condi-
O tioning. Its primary function is to convert the Hall signal infor-
Channel1 Signal
Tracker1(S/H_max)
Tracker1(S/H_min)
0
Figure 3. Signal Acquisition From a Power On or Stopped (no
field) Condition
mation of zero crossings, signal amplitude, and direction, into a
single bit pulse width modulated signal.
The leading edge of the pulse is determined by a zero crossing
event from Tracker 1. The duration of the pulse is determined
by direction and signal amplitude. (See Fig. 4 and 5)
All events within the signal conditioning are synchronized to
the internal clock. Asynchronous zero cross events are aligned
to the following clock edge which results in a maximum delay
of 1. 4 us. Output pulse widths are modulated by means of a 19
bit counter. The counter functions both as a pulse width modula-
-4-
REV. PrA
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