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AD1317KZ

Ultrahigh Speed Window Comparator with Latch

Analog Devices 

AD1317

DEFINITION OF TERMS

Vos

INPUT OFFSET VOLTAGE—The voltage that

must be applied between either VINA and VINA/B or

VINB and VINA/B to obtain zero voltage between

outputs QA and QA, or QB and QB, respectively.

dVOS/dT OFFSET DRIFT—The ratio of the change in input

offset voltages, over the operating temperature range,

to the change in temperature.

Ibca

INPUT BIAS CURRENT (VINA/B, ACTIVE)—

The bias current of the window comparator’s com-

mon input with inputs enabled.

Ibci

INPUT BIAS CURRENT (VINA/B, INHIBIT)—

The bias current of the window comparator’s com-

mon input with inputs inhibited.

Ibsa

INPUT BIAS CURRENT (VINA or VINB,

ACTIVE)—The bias current of either single input

with inputs active.

Ibsi

INPUT BIAS CURRENT (VINA or VINB,

INHIBIT)—The bias current of either single input

with inputs inhibited.

Rinc

INPUT RESISTANCE (VINA/B)—The input

resistance looking into the window comparator’s

common input.

Rins INPUT RESISTANCE (VINA or VINB)—The

input resistance looking into either single input.

CIN

INPUT CAPACITANCE (VINA/B)—The capaci-

tance looking into the window comparator’s common

input.

VCM

INPUT COMMON-MODE VOLTAGE RANGE—

The range of voltages on the input terminals for

which the offset and propagation delay specifications

apply.

VDIFF

INPUT DIFFERENTIAL VOLTAGE RANGE—

The maximum difference between any input terminal

voltages.

CMRR

COMMON-MODE REJECTION RATIO—The

ratio of common-mode input voltage range to the

peak-to-peak change in input offset voltage over this

range.

IIH

LOGIC “1” INPUT CURRENT—The logic high

current flowing into (+) or out of (–) a logic input.

IIL

LOGIC “0” INPUT CURRENT—The logic low

current flowing into (+) or out of (–) a logic input.

VOH

LOGIC “1” OUTPUT VOLTAGE—The logic high

output voltage with a specified load.

VOL

IOH

IOL

I+

I–

PSRR

LOGIC “0” OUTPUT VOLTAGE—The logic low

output voltage with a specified load.

LOGIC “1” OUTPUT CURRENT—The logic high

output source current.

LOGIC “0” OUTPUT CURRENT—The logic low

output source current.

POSITIVE SUPPLY CURRENT—The current

required from the +VS supply.

NEGATIVE SUPPLY CURRENT—The current

required from the –VS supply.

POWER SUPPLY REJECTION RATIO—The ratio

of power supply voltage change to the peak-to-peak

change in input offset voltage.

AD1317 SWITCHING TERMS (See Figure 3)

tPDR

INPUT TO OUTPUT RISING EDGE DELAY—

The propagation delay measured from the time

VINA/B crosses either VINA or VINB, in a low to

high transition, to the time QA and QA or QB and

QB cross, respectively.

tPDF

INPUT TO OUTPUT FALLING EDGE DELAY—

The propagation delay measured from the time

VINA/B crosses either VINA or VINB, in a high to

low transition, to the time QA and QA or QB and

QB cross, respectively.

tS

MINIMUM LATCH SET-UP TIME—The minium

time before LE goes high with respect to LE that an

input signal change must be present in order to be

acquired and held at the outputs.

tH

MINIMUM LATCH HOLD TIME—The minium

time after LE goes high with respect to LE that the

input signal must remain unchanged in order to be

acquired and held at the outputs.

tPW

MINIMUM LATCH ENABLE PULSE WIDTH—

The minimum time that LE must be held high with

respect to LE in order to acquire and hold an input

change.

tLO

LATCH ENABLE TO OUTPUT DELAY—The

time between when LE goes high with respect to LE

that QA and QA or QB and QB cross.

tID

INPUT STAGE DISABLE TIME—The time be-

tween when IE goes high with respect to IE that the

input bias currents drop to 10% of their nominal

value.

tIE

INPUT STAGE ENABLE TIME—The time be-

tween when IE goes high with respect to IE that the

input bias currents rise to 90% of their nominal values.

–4–

REV. A

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