ACS8527 Ver la hoja de datos (PDF) - Semtech Corporation
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ACS8527 Datasheet PDF : 22 Pages
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ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 4 Hardware Configuration for Selecting Expected After initialization, the output clocks are stable and the
Input Frequency on SEC1 and SEC2
device will operate as a simple switch, with the DPLL
IP_FREQ Pins
2
1
0
0
0
0
SONSDHB Input frequency
Pin
X
8 kHz
trying to lock on to the selected reference source.
Output Clock Phase Continuity on Source
Switchover
0
2.048 MHz
0
0
1
1
1.544 MHz
0
1
0
X
6.48 MHz
0
1
1
X
19.44 MHz
1
0
0
X
25.92 MHz
1
0
1
X
38.88 MHz
1
1
0
X
51.84 MHz
1
1
1
X
77.76 MHz
Preconfiguring Inputs - SONET/SDH
The SONSDHB pin is used to select SDH or SONET mode
for the entire device and its setting affects parameters
other than just the expected input frequency selection,
e.g. output frequency. To set the device for use in a SONET
network, set SONSDHB high. For SDH, set SONSDHB low.
Selection of Input SECs
Initialization
Switching between inputs SEC1 and SEC2 is triggered
directly from a dedicated pin (SRCSW), though for the
device to operate properly, the device must first be
initialized by holding the pin High during reset and for at
least a further 251 ms after PORB has gone High (250 ms
allowance for the internal reset to be removed plus 1 ms
allowance for APLLs to start-up and become stable). If
SCRSW is held Low at any time during the 251 ms
initialization period, this will result in incorrect device
operation. A simple external circuit to set SCRSW high for
the required period is shown in the “Simplified Application
Schematic” on page 18.
SEC Selection - SRCSW pin
A phase offset between SEC inputs will be seen as a
phase shift on the output on source switchover equal to
the input phase offset. (Note...The ACS8527 has no
Phase Build-out function to accommodate this. If this
function is required, it is available on the AS8525 LC/P
device).
The rate of change of phase on the output, during the time
between input switchover and the output settling to a
steady state, is dependent on input frequency, and input
phase change. The ACS8527 always complies with
GR-1244-CORE[13] spec for Stratum 3 (max rate of phase
change of 81ns/1.326 ms), for input frequencies at
6.48 MHz or higher.
For inputs at a lower frequency than 6.48 MHz (e.g. 8
kHz), then to ensure compliance with GR-1244-CORE[13],
the input phase difference between the Master and Slave
inputs to the line card PLL should be limited to less than
190 ns. A well designed system would have master and
slave clock from the clock sync cards aligned to within a
few nanoseconds. In which case a complete system using
the Semtech SETS clock card parts (ACS8530, ACS8520
or ACS8510) and this line card part would be fully
compliant to GR-1244-CORE[13] specifications under all
conditions due to the lower frequency range and
bandwidth set at the clock card end.
Phase Locked Loops (PLLs)
The PLL circuitry (See Figure 1) is represented by a DPLL
and an output multiplying and filtering APLL. The device is
more complex than the representation suggests, with
several DPLLs and APLLs being used in different
configurations to provide a range of frequencies at the
outputs, with the internal configuration optimizing for
jitter filtering and wander tracking. The output
frequencies available are shown in Table 6.
After the ACS8527 has been initialized (see previous
“Initialization” section), then the value of SRCSW pin
directly selects either SEC1 (SRCSW High) or SEC2
(SRCSW Low). The frequency tolerance of SEC1 and SEC2
is ± 80 ppm with respect to the local oscillator clock.
The DPLL initially tries to lock to the input frequency of the
selected input SEC. It uses a wide “acquisition” bandwidth
setting until it has achieved frequency lock, then the DPLL
switches to using a narrower “tracking” (locked)
bandwidth setting as it locks to the phase of the input.
Revision 4.01/June 2006 © Semtech Corp.
Page 7
www.semtech.com
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