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Número de pieza

componentes Descripción

Fabricante

ACS8527

Line Card Protection Switch for PDH, SONET or SDH Systems

Semtech Corporation 

ACS8527 MUXPLL

ADVANCED COMMUNICATIONS

Table 3 Other Pins

FINAL

DATASHEET

Pin Number

Symbol

I/O

Type

Description

5

LOS_ALARM

O

TTL/CMOS Loss Of Signal Alarm: Flag to indicate loss of activity of currently selected

reference source is raised on this pin.

6

REFCLK

I

TTL

Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock).

13

SRCSW

I

TTLD

Source Switching: Controls switchover between SEC1 and SEC2 inputs as the

selected reference. SRCSW must be held High on power-up or reset, and for a

further 251 ms after PORB has gone High. See “Initialization” on page 7.

17

FrSync

O

TTL/CMOS Output Reference: 8 kHz Frame Sync output.

18

MFrSync

O

TTL/CMOS Output Reference: 2 kHz Multi-Frame Sync output.

19,

O1POS,

20

O1NEG

O

LVDS

Output Reference 1: Differential output. LVDS.

28

IP_FREQ0

I

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

29

SEC1

I

TTLD

Input Reference 1: Primary input.

30

SEC2

I

TTLD

Input Reference 2: Secondary input.

33

IP_FREQ1

I

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

34

IP_FREQ2

I

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

35

O2_FREQ0

I

TTLD

Output O2 Frequency Select: Frequency select for output O2.

36

O2_FREQ2

I

TTLD

Output O2 Frequency Select: Frequency select for output O2.

37

TRST

I

TTLD

JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.

TRST = 0 for normal device operation (JTAG logic transparent). NC if not used.

38

O2_FREQ1

I

TTLD

Output O2 Frequency Select: Frequency select for output O2.

41

TMS

I

TTLD

JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK.

NC if not used.

45

O1_FREQ0

I

TTLU

Output O1 Frequency Select: Frequency select for output O1.

46

O1_FREQ1

I

TTLU

Output O1 Frequency Select: Frequency select for output O1.

48

PORB

I

TTLU

Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset

back to default values.

49

TCK

50

TDO

I

TTLD

JTAG Clock: Boundary Scan clock input.

O

TTL/CMOS JTAG Output: Serial test data output. Updated on falling edge of TCK.

51

TDI

I

TTLD

JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used.

56

O2

O

TTL/CMOS Output Reference: Programmable, default 19.44 MHz.

63

O1_FREQ2

I

TTLU

Output O1 Frequency Select: Frequency select for output O1.

64

SONSDHB

I

TTLD

SONET or SDH frequency select: Sets the device for SONET or SDH frequencies

on power-up/reset.

Revision 4.01/June 2006 © Semtech Corp.

Page 5

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