ACS8526 Ver la hoja de datos (PDF) - Semtech Corporation

Número de pieza

componentes Descripción

Fabricante

ACS8526

Line Card Protection Switch for PDH, SONET or SDH Systems

Semtech Corporation 

ACS8526 LC/P LITE

ADVANCED COMMUNICATIONS

Table 3 Other Pins (cont...)

FINAL

DATASHEET

Pin Number

Symbol

I/O

Type

Description

18

MFrSync

O

TTL/CMOS Output Reference: 2 kHz Multi-Frame Sync output.

19,

O1POS,

20

O1NEG

O LVDS/PECL Output Reference 1: Differential output., default LVDS.

28

IP_FREQ0

I

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

29

SEC1

I

TTLD

Input Reference 1: Primary input.

30

SEC2

I

TTLD

Input Reference 2: Secondary input.

33

IP_FREQ1

I

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

34

IP_FREQ2

I

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

35

O2_FREQ0

I

TTLD

Output O2 Frequency Select: Frequency select for output O2.

36

O2_FREQ2

I

TTLD

Output O2 Frequency Select: Frequency select for output O2.

37

TRST

I

TTLD

JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.

TRST = 0 for normal device operation (JTAG logic transparent). NC if not used.

38

O2_FREQ1

I

TTLD

Output O2 Frequency Select: Frequency select for output O2.

41

TMS

I

TTLD

JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK.

NC if not used.

42

CLKE

I

TTLD

SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of

SCLK to be active.

43

SDI

44

CSB

I

TTLD

Interface Address: SPI compatible Serial Data Input.

I

TTLU

Chip Select (Active Low): This pin is asserted Low by the external device

(microprocessor) to enable the Serial interface.

45

O1_FREQ0

I

TTLU

Output O1 Frequency Select: Frequency select for output O1.

46

O1_FREQ1

I

TTLU

Output O1 Frequency Select: Frequency select for output O1.

47

SCLK

48

PORB

I

TTLD

Serial Data Clock: The Low to High transition on this input latches the data on the

SDI input into the internal registers. The active clock edge (defined by CLKE)

latches the data out of the internal registers onto the SDO output.

I

TTLU

Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset

back to default values.

49

TCK

50

TDO

I

TTLD

JTAG Clock: Boundary Scan clock input.

O

TTL/CMOS JTAG Output: Serial test data output. Updated on falling edge of TCK.

51

TDI

I

TTLD

JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used.

52

SDO

O

TTLD

Interface Address: SPI compatible Serial Data Output.

56

O2

O

TTL/CMOS Output Reference: Programmable, default 19.44 MHz.

63

O1_FREQ2

I

TTLU

Output O1 Frequency Select: Frequency select for output O1.

64

SONSDHB

I

TTLD

SONET or SDH frequency select: Sets the initial power-up state (or state after a

PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and

Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. The register states can be changed after

power-up by software. When set Low, SDH rates are selected (2.048 MHz etc.)

and when set High, SONET rates are selected (1.544 MHz etc.) The register

states can be changed after power-up by software.

Revision 4.01/June 2006 © Semtech Corp.

Page 5

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