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ACS8526

Line Card Protection Switch for PDH, SONET or SDH Systems

Semtech Corporation 

ACS8526 LC/P LITE

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

range of output frequencies and levels of jitter

divided to 8 kHz and this will ensure synchronization of

performance. However if the device is configured by

frequencies, from 8kHz upwards, within the two DPLLs.

hardware alone, then the PLLs are configured as shown in

Table 7 and 8.

Both of the DPLLs’ outputs can be connected to

Digital Synthesis is used to generate all required

SONET/SDH output frequencies. The digital logic

operates at 204.8 MHz that is multiplied up from the

external 12.800 MHz oscillator module. Hence the best

resolution of the output signals from the DPLLs is one

204.8 MHz cycle or 4.9 ns.

Additional resolution and lower final output jitter is

multiplying and filtering APLLs. The outputs of these

APLLs are divided making a number of frequencies

simultaneously available for selection at the output clock

ports. The various combinations of DPLL, APLL and divider

configurations allow for generation of a comprehensive

set of frequencies, as listed in Table 9, “Output Frequency

Selection,” on page 19.

provided by a de-jittering APLL that reduces the 4.9 ns p-p

jitter from the digital down to 500 ps p-p and 60 ps RMS

as typical final outputs measured broadband (from 10 Hz

to 1 GHz). This arrangement combines the advantages of

the flexibility and repeatability of a DPLL with the low jitter

of an APLL.

A function is provided to synchronize the lower output

frequencies when DPLL1 is locked to a high frequency

reference input. The dividers that generate the 2 kHz and

8 kHz outputs are reset such that the output 2/8 kHz

clocks are lined up with the input 2 kHz.

The DPLLs in the ACS8526 are programmable for

parameters of bandwidth (18, 35 and 70 Hz) and

damping factor (from 1.2 to 20). See Sections “DPLL1

Jitter Transfer Characteristic, (Freq. = 1.544 MHz, Jitter =

0.2 UI p-p, Damping Factor = 5)” on page 14, and

“Damping Factor Programmability” on page 15.

DPLL1 input frequency is programmable with 12 common

SONET/SDH spot frequencies. See

cnfg_nominal_frequency Reg. 3C and Reg. 3D

The DPLL has programmable frequency acceptance and

output range (from 0 to 80 ppm) set by the allowable

offset between the expected input frequency and the

calibrated external frequency, Reg. 41 and Reg. 42).

There is no requirement to understand the loop filter

equations or detailed gain parameters since all high level

factors such as overall bandwidth can be set directly in

registers via the microprocessor interface. No external

critical components are required for either the internal

DPLLs or APLLs, providing another key advantage over

traditional discrete designs.

The PLL configurations required for particular output

frequencies are described in “Output Frequency Selection

by Hardware” on page 17, and “Output Frequency

Selection by Register Programming” on page 17.

An advanced feature of the device is its ability to control

the amount of jitter and wander that is tolerated on the

input. This is achieved by the configuration of the Phase

and Frequency detectors within the DPLLs, which

determines the phase error input to the Digital Loop Filter.

For basic operation, the configuration should not be

changed from the default settings.

PLL Architecture

Figure 4 shows the PLL arrangement in more detail. Each

DPLL comprises a generic Phase and Frequency Detector

(PFD) with a Digital Loop filter, together with Forward,

Feedback, and Low Frequency (LF) (DPLL1 only) Digital

Frequency Synthesis (DFS) blocks. The Forward DFS block

represents a Digital Timed Oscillator (DTO).

DPLL1 always produces an output at 77.76 MHz to feed

the APLL, regardless of the frequency selected at the

output pins or the locking frequency (frequency at the

input of the Phase and Frequency Detector- PFD).

DPLL2 can be operated at a number of frequencies. This

is to enable the generation of extra output frequencies,

which cannot be easily related to 77.76 MHz. If DPLL2 is

enabled, it locks to the 8 kHz from DPLL1. This is because

all of the frequencies of operation of DPLL2 can be

The DPLL architecture for DPLL1 is more complex than

that of DPLL2. See “DPLL Feature Summary” on page 16..

The selected SEC input is always supplied to DPLL1.

DPLL1 may use either digital feedback or analog

feedback (via APLL3).

DPLL2 always takes its feed from DPLL1 and cannot be

used to select a different input to that of DPLL1.

Revision 4.01/June 2006 © Semtech Corp.

Page 11

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