ACS8525 Ver la hoja de datos (PDF) - Semtech Corporation
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ACS8525 Datasheet PDF : 112 Pages
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ACS8525 LC/P
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Specifications” on page 98 for more information on
Table 4 gives details of the input reference ports, showing
electrical compatibility.
the input technologies and the range of frequencies
Input frequencies supported range from 2 kHz to
155.52 MHz. Common E1, DS1, OC-3 and sub-divisions
are supported as spot frequencies that the DPLLs will
supported on each port; the default spot frequencies and
default priorities assigned to each port on power-up or by
reset are also shown.
directly lock to. Any input frequency, up to 100 MHz, that
is a multiple of 8 kHz can also be locked to via an inbuilt
programmable divider.
SDH and SONET networks use different default
frequencies; the network type is selectable using the
cnfg_input_mode Reg. 34 Bit 2, ip_sonsdhb.
Preconfiguring Inputs
Each input device has to be preconfigured with:
z Expected input frequency cnfg_ref_source_frequency
register (Reg. 22 to 25 and Reg. 28)
z Technology (TTL or PECL/LVDS) where applicable, via
cnfg_differential_inputs (Reg. 36)
z Selection Priority (Reg. 19, 1A and 1C).
z For SONET, ip_sonsdhb = 1
z For SDH, ip_sonsdhb = 0
On power-up or by reset, the default will be set by the state
of the SONSDHB pin (pin 64). Specific frequencies and
priorities are set by configuration.
The frequency selection is programmed via the
cnfg_ref_source_frequency register (Reg. 22 - Reg. 28).
Table 4 Input Reference Source Selection and Priority Table
Port Name Channel
Number (Bin)
Input Port
Technology
SEC1 TTL 0011
TTL/CMOS
SEC2 TTL 0100
TTL/CMOS
SEC1 DIFF 0101
SEC2 DIFF 0110
SYNC1
SYNC2
SEC3
0111
1000
1001
PECL/LVDS
PECL default
PECL/LVDS
PECL default
TTL/CMOS
TTL/CMOS
TTL/CMOS
SYNC3
1010
TTL/CMOS
Frequencies Supported
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 155.52 MHz (see Note (ii))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 155.52 MHz (see Note (ii))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
2/4/8 kHz auto-sensing
2/4/8 kHz auto-sensing
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
2/4/8 kHz auto-sensing
Default
Priority
2
3
0
0
n/a
n/a
4
n/a
Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being
77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 Bit 2, ip_sonsdhb).
(ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz (and 311.04 MHz for Output O1 only).
(iii) SEC1 TTL and SEC2 TTL ports are on pins SEC1 and SEC2. SEC1 DIFF (Differential) port uses pins SEC1POS and SEC1NEG, similarly
SEC2DIFF uses pins SEC2POS and SEC2NEG.
Revision 3.01/August 2005 © Semtech Corp.
Page 8
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