ACS8525 Ver la hoja de datos (PDF) - Semtech Corporation
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ACS8525 Datasheet PDF : 112 Pages
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ACS8525 LC/P
ADVANCED COMMUNICATIONS
Table 3 Other Pins (cont...)
FINAL
DATASHEET
Pin Number
Symbol
I/O
17
FrSync
O
18
MFrSync
O
19,
O1POS,
O
20
O1NEG
23,
SEC1_POS,
I
24
SEC1_NEG
25,
SEC2_POS,
I
26
SEC2_NEG
28
SYNC1
I
29
SEC1
I
30
SEC2
I
33
SYNC2
I
34
SEC3
I
35
SYNC3
I
37
TRST
I
41
TMS
I
42
CLKE
I
43
SDI
I
44
CSB
I
47
SCLK
I
48
PORB
I
49
TCK
I
50
TDO
O
51
TDI
I
52
SDO
O
56
O2
O
64
SONSDHB
I
Type
TTL/CMOS
TTL/CMOS
LVDS/PECL
PECL/LVDS
PECL/LVDS
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLU
TTLD
TTLU
TTLD
TTL/CMOS
TTLD
TTLD
TTL/CMOS
TTLD
Description
Output Reference: 8 kHz Frame Sync output.
Output Reference: 2 kHz Multi-Frame Sync output.
Output Reference: Programmable, default 38.88 MHz, LVDS.
Input Reference: Programmable, default 19.44 MHz, PECL.
Input Reference: Programmable, default 19.44 MHz PECL.
(Master) Multi-Frame Sync 2kHz Input: Connect to 2 or 8 kHz
Multi-Frame Sync output of Master SETS.
(Master) Input Reference: Programmable, default 8 kHz.
(Slave) Input Reference: Programmable, default 8 kHz.
(Slave) Multi-Frame Sync 2 kHz: Connect to 2 or 8 kHz Multi-Frame Sync
output of Slave SETS.
(Stand-by) Input Reference: External stand-by reference clock source,
programmable, default 19.44MHz.
(Stand-by) Input Reference: External stand-by 2 or 8 kHz Multi-Frame
Sync clock source.
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan
mode. TRST = 0 is Boundary Scan stand-by mode, still allowing normal
device operation (JTAG logic transparent). NC if not used.
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge
of TCK. NC if not used.
SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling
edge of SCLK to be active.
Serial Interface Address: Serial Data Input.
Chip Select (Active Low): This pin is asserted Low by the microprocessor
to enable the microprocessor interface.
Serial Data Clock. When this pin goes High data is latched from SDI pin.
Power-On Reset: Master reset. If PORB is forced Low, all internal states
are reset back to default values.
JTAG Clock: Boundary Scan clock input.
JTAG Output: Serial test data output. Updated on falling edge of TCK.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK.
Interface Address: SPI compatible Serial Data Output.
Output Reference: Programmable, default 19.44 MHz.
SONET or SDH Frequency Select: Sets the initial power-up state (or
state after a PORB) of the SONET/SDH frequency selection registers,
Reg. 34, Bit 2 and Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. When set Low,
SDH rates are selected (2.048 MHz etc.) and when set High, SONET
rates are selected (1.544 MHz etc.) The register states can be changed
after power-up by software.
Revision 3.01/August 2005 © Semtech Corp.
Page 6
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