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ACS8522A

Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

Semtech Corporation 

ACS8522A SETS LITE

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Introduction

The ACS8522A is a highly integrated, single-chip solution

for the SETS function in a SONET/SDH Network Element,

for the generation of SEC and Frame/MultiFrame sync

confines all temperature critical components to one well

defined and pre-calibrated module, whose performance

can be chosen to match the application; for example an

TCXO for Stratum 3 applications.

pulses. Digital Phase Locked Loop (DPLL) and direct

digital synthesis methods are used in the device so that

the overall PLL characteristics are very stable and

consistent compared to traditional analog PLLs.

All performance parameters of the DPLLs are

programmable without the need to understand detailed

PLL equations. Bandwidth, damping factor and lock range

can all be set directly, for example. The PLL bandwidth

In Free-run mode, the ACS8522A generates a stable, low-

noise clock signal at a frequency to the same accuracy as

the external oscillator, or it can be made more accurate

can be set over a wide range, 0.1 Hz to 70 Hz in 18 steps,

to cover all SONET/SDH clock synchronization

applications.

via software calibration to within 0.02 ppm. In Locked

mode, the ACS8522A selects the most appropriate input

reference source and generates a stable, low-noise clock

signal locked to the selected reference. In Holdover mode,

The ACS8522A includes a serial port, providing access to

the configuration and status registers for device setup

and monitoring.

the ACS8522A generates a stable, low-noise clock signal,

adjusted to match the last known good frequency of the General Description

last selected reference source. A high level of phase and

frequency accuracy is made possible by an internal

resolution of up to 54 bits and internal Holdover accuracy

of 0.0012 ppb (1.2 x 10-12). In all modes, the frequency

accuracy, jitter and drift performance of the clock meet

the requirements of ITU G.736[7], G.742[8], G783[9],

G.812[10], G.813[11], G.823[13],G.824[14] and Telcordia

GR-253-CORE[17] and GR-1244-CORE[19].

The ACS8522A supports all three types of reference clock

source: recovered line clock, PDH network

synchronization timing and node synchronization. The

ACS8522A generates independent T0 and T4 clocks, an

8 kHz Frame Synchronization clock and a 2 kHz

Multi-Frame Synchronization clock.

One key architectural advantage that the ACS8522A has

over traditional solutions is in the use of DPLL technology

for precise and repeatable performance over temperature

or voltage variations and between parts. The overall PLL

bandwidth, loop damping, pull-in range and frequency

accuracy are all determined by digital parameters that

provide a consistent level of performance. An Analog PLL

(APLL) takes the signal from the DPLL output and provides

a lower jitter output. The APLL bandwidth is set four orders

of magnitude higher than the DPLL bandwidth. This

ensures that the overall system performance still

Overview

The following description refers to the Block Diagram

(Figure 1 on page 1).

The ACS8522A SETS device has four SEC clock inputs

(SEC1 to SEC4), and generates four output clocks on

outputs O1 to O4. The device offers a total of 55 possible

output frequencies. There are two independent paths

through the device: T0 path comprising T0 DPLL and T0

Output and Feedback APLLs, and T4 path comprising T4

DPLL and T4 Output APLL.

The T0 path is a high quality, highly configurable path

designed to provide features necessary for node timing

synchronization within a SONET/SDH network. The T4

path is a simpler and less configurable path designed to

give a totally independent path for internal equipment

synchronization. The device supports use of either or both

paths, either locked together or independent.

The four SEC inputs ports are TTL/CMOS, 3 V compatible

(with clamping if required by connecting the VDDCLMP

pin). Refer to the electrical characteristics section for

more information on the electrical compatibility and

details. Input frequencies supported range from 2 kHz to

maintains the advantage of consistent behavior provided 100 MHz.

by the digital approach.

Common E1, DS1, OC3 and sub-divisions are supported

The DPLLs are clocked by the external Oscillator module as spot frequencies that the DPLLs will directly lock to.

(TCXO or OCXO) so that the Free-run or Holdover

Any input frequency, up to 100 MHz, that is a multiple of

frequency stability is only determined by the stability of 8 kHz can also be locked to via an inbuilt programmable

the external oscillator module. This second key advantage divider.

Revision 1.00/September 2007 © Semtech Corp.

Page 7

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