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AAT4292

Seven Channel High-Side I/O Expander

Analog Technology Inc 

SmartSwitchTM

Application Information

Thermal Considerations

The AAT4292 is designed to deliver continuous output

load currents. Due to its high integration, care must be

taken in designing for higher load conditions. If greater

loads are required, outputs can be tied together to

deliver higher power to a given load.

For the thermal calculation, assuming that the total cur-

rent capability of the seven channels is ITOTAL, each chan-

nel

has

the

same

current

which

is

, IOUT

=

ITOTAL

7

then

PTOTAL = 7IOUT2RDS(ON) = 7

ITOTAL

7

2

RDS(ON) = PD - PDERATE(TA - 25)

Where:

PD = 440mW when TA = 25°C

PDERATE = 4.4mW/°C

RDS(ON) = 1.7Ω (maximum) when VIN = 5.0V

For example, at 25oC ambient, the AAT4292 power capa-

bility is PTOTAL = 440mW, then ITOTAL ≅ 1.35A at VIN = 5.0V.

The current capability for each channel is IOUT = 192mA.

At 85oC ambient, the AAT4292 power capability is PTOTAL

= 440 - (85 - 25)4.4 = 176mW, then ITOTAL ≅ 0.85A at VIN

= 5.0V. The current capability for each channel is IOUT =

121mA.

Output Sequencing

If output sequencing is not necessary, then a pulse burst

of 33 address clocks followed by 1 data clock will switch

on all of the outputs simultaneously. Alternately, the

OUT3 to OUT7 will be switched on simultaneously on the

first rising edge of the EN/SET pin after the tLAT timeout.

PRODUCT DATASHEET

AAT4292

Seven Channel High-Side I/O Expander

Output sequencing is accomplished via a series of pulses

on the EN/SET pin. Each time a new pulse burst is

asserted on EN/SET, the AAT4292 internal clock counter

starts to count and sends the counted clock number to

the register. After the tLAT timeout, the internal clock

counter is reset and waits for the next pulse burst. For

example, to sequence the outputs in order from OUT1 to

OUT7, seven clock bursts are input on the EN/SET pin.

From Table 1 and Table 2, the first bust of 34 address

clocks followed by 32 data clocks turns on OUT1. The

next burst of 33 address clocks followed by 32 data

clocks will add OUT2. Then the burst of 33 address

clocks followed by 16 data clocks will add OUT3; the

burst of 33 address clocks followed by 8 data clocks will

add OUT4; the burst of 33 address clocks followed by 4

data clocks will add OUT5; the burst of 33 address clocks

followed by 2 data clocks will add OUT6; the burst of 33

address clocks followed by 1 data clock will add OUT7.

Likewise, the outputs can be turned on/off in any order

by adding the corresponding clock bursts.

Input Capacitor

Normally, the input capacitor value could be ten times

that of the total load capacitors. If the device outputs

OUT1 to OUT7 have capacitor loads, depending on the

load capacitor value, it is recommended that a 1μF to

10μF 0603 or 0805 ceramic capacitor be placed as close

as possible between VIN and GND. For example, if the

capacitor load at each output is 0.1μF, the Murata

GRM21BR61C106K ceramic capacitor (10μF/16V/0805/

X5R) or a similar capacitor could be used. This helps to

provide a low impendence loop to charge the load capac-

itors during the MOSFET switches' turn-on transient and

keep the VIN voltage stable.

4292.2008.08.1.0

www.analogictech.com

11

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