A6801(2009) Ver la hoja de datos (PDF) - Allegro MicroSystems

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Fabricante

A6801
(Rev.:2009)

DABiC-5 Latched Sink Drivers

Allegro MicroSystems 

A6800 and

A6801

DABiC-5 Latched Sink Drivers

Timing Requirements and Specifications

(Logic Levels are VDD and Ground)

CLEAR

STROBE

INN

OUTN

A

CB

H

CB

D

E

G

F

A

C

B

H

E

OUTPUT ENABLE

OUT N

50%

t dis(BQ)

10%

HIGH = ALL OUTPUTS DISABLED (OFF)

t en(BQ)

tr

DATA

tf

90%

50%

Key

A

B

C

D

E

F

G

H

tdis(BQ)

ten(BQ)

Description

Minimum data active time before Strobe enabled (Data Set-Up Time)

Minimum data active time after Strobe disabled (Data Hold Time)

Minimum Strobe pulse width

Maximum time between Strobe activation and transition from output on to output off*

Maximum time between Strobe activation and transition from output off to output on*

Maximum time between Clear activation and transition from output on to output off*

Minimum Clear pulse width

Minimum data pulse width

Output Enable to output off delay*

Output Enable to output on delay*

*Conditions for output transition testing are: VCC = 50 V, VDD = 5 V, R1 = 500 Ω, C1 ≤ 30 pF.

Time (ns)

25

25

50

500

500

500

50

100

500

500

NOTE: Information present at an input is transferred

to its latch when the STROBE is high. A high CLEAR

input will set all latches to the output off condition

regardless of the data or STROBE input levels. A high

OUTPUT ENABLE will set all outputs to the off con-

tdition, regardless of any other input conditions. When

the OUTPUT ENABLE is low, the outputs depend on

the state of their respective latches.

Allegro MicroSystems, Inc.

5

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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