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A4975

Full-Bridge PWM Microstepping Motor Driver

Allegro MicroSystems 

A4975

Full-Bridge PWM Microstepping Motor Driver

Functional Description

Two A4975 full-bridge PWM microstepping motor drivers are

needed to drive the windings of a bipolar stepper motor. Internal

pulse width modulated (PWM) control circuitry regulates each

motor winding current. The peak motor current is set by the

value of an external current-sense resistor (RS), a reference

voltage (VREF), and the digital-to-analog converter (DAC) data

inputs (D0, D1, and D2).

To improve motor performance, especially when using

sinusoidal current profiles necessary for microstepping, the

A4975 has three distinct current-decay modes: slow decay, fast

decay, and mixed decay.

PHASE Input. The PHASE input controls the direction of

current flow in the load (table 1). An internally generated dead

time of approximately 500 ns prevents crossover currents that

could occur when switching the PHASE input.

DAC Data Inputs (D0, D1, D2). A non-linear DAC is used

to digitally control the output current. The output of the DAC is

used to set the trip point of the current-sense comparator. Table 3

shows DAC output voltages for each input condition. When D0,

D1, and D2 are all logic low, all of the power output transistors

are turned off.

Internal PWM Current Control. Each motor driver

contains an internal fixed off-time PWM current-control circuit

that limits the load current to a desired value (ITRIP). Initially,

a diagonal pair of source and sink transistors are enabled and

current flows through the motor winding and RS (figure 1). When

the voltage across the sense resistor equals the DAC output

voltage the current-sense comparator resets the PWM latch,

VBB

which turns off the source drivers (slow-decay mode) or the sink

and source drivers (fast- or mixed-decay mode).

With the DAC data input lines at VIN(1) voltage, the maximum

value of current limiting is set by the selection of RS and VREF

with a transconductance function approximated by:

ITRIP ≈ VREF / 5RS.

The actual peak load current (IPEAK) will be slightly higher than

ITRIP due to internal logic and switching delays. The driver(s)

remain off for a time period determined by a user-selected

external resistor-capacitor combination (RTCT). At the end of

the fixed off-time, the driver(s) are re-enabled, allowing the load

current to increase to ITRIP again, maintaining an average load

current.

The DAC data input lines are used to provide up to eight levels

of output current. The internal 3-bit digital-to-analog converter

reduces the reference input to the current-sense comparator

in precise steps (the step reference current ratio or SRCR) to

provide half-step, quarter-step, or “microstepping” load-current

levels.

ITRIP ≈ SRCR x VREF / 5RS

Slow Current-Decay Mode. When VPFD ≥ 3.5 V, the

device is in slow current-decay mode (the source drivers are

disabled when the load current reaches ITRIP). During the fixed

off-time, the load inductance causes the current to recirculate

through the motor winding and sink drivers (see figure 1).

Slow-decay mode produces low ripple current for a given fixed

off-time (see figure 2). Low ripple current is desirable because

the average current in the motor winding is more nearly equal

to the desired reference value, resulting in increased motor

I PEAK

PFD

SLOW (VPFD ≥ 3.5 V)

MIXED (1.1 V ≤ V PFD≤ 3.1 V)

FAST (VPFD ≤ 0.8 V)

RS

Drive Current (Normal)

Recirculation (Fast Decay)

Recirculation (Slow Decay)

Figure 1 — Load-Current Paths

t OFF

Dwg. WP-031-1

Figure 2 — Current-Decay Waveforms

Allegro MicroSystems, Inc.

6

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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