Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Decoupling Capacitance between VDD and VSS
CDC1
Decoupling Capacitance between VDDQ and VSSQ
CDC2
Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Value
0.1 + 0.01
0.1 + 0.01
A43L2616B
Unit
μF
μF
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0°C to 70°C TA = -40ºC to +85ºC)
Symbol
Parameter
Test Conditions
Icc1
Icc2 P
Icc2 PS
Operating Current
(One Bank Active)
Burst Length = 1
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA
Precharge Standby Current CKE ≤ VIL(max), tCC = 15ns
in power-down mode
CKE ≤ VIL(max), tCC = ∞
Speed
-6
-7
70
70
2
1
ICC2N
ICC2NS
ICC3N
ICC4
ICC5
Precharge Standby Current
in non power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable.
Active Standby current in
non power-down mode
(One Bank Active)
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
Operating Current
(Burst Mode)
IOL = 0mA, Page Burst
All bank Activated, tCCD = tCCD (min)
Refresh Current
tRC ≥ tRC (min)
20
15
30
100
100
130
130
ICC6 Self Refresh Current
CKE ≤ 0.2V
1.5
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).
Unit Notes
mA
1
mA
mA
mA
mA
1
mA
2
mA
(December, 2009, Version 1.3)
5
AMIC Technology, Corp.