A25L016 Ver la hoja de datos (PDF) - AMIC Technology

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A25L016

(A25L010 - A25L512) Serial Flash Memory

AMIC Technology 

A25L016 Series

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of

the device, most significant bit first.

Serial Data Input (DIO) is sampled on the first rising edge of

Serial Clock (C) after Chip Select ( S ) is driven Low. Then, the

one-byte instruction code must be shifted in to the device,

most significant bit first, on Serial Data Input (DIO), each bit

being latched on the rising edges of Serial Clock (C).

The instruction set is listed in Table 3.

Every instruction sequence starts with a one-byte instruction

code. Depending on the instruction, this might be followed by

address bytes, or by data bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at

Higher Speed (Fast_Read), Read Identification (RDID), Read

Electronic Manufacturer and Device Identification (REMS),

Read Status Register (RDSR) or Release from Deep

Power-down, Read Device Identification and Read Electronic

Signature (RES) instruction,

the shifted-in instruction sequence is followed by a data-out

sequence. Chip Select ( S ) can be driven High after any bit of

the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Block

Erase (BE), Chip Erase (CE), Write Status Register (WRSR),

Write Enable (WREN), Write Disable (WRDI) or Deep

Power-down (DP) instruction, Chip Select ( S ) must be driven

High exactly at a byte boundary, otherwise the instruction is

rejected, and is not executed. That is, Chip Select ( S ) must

driven High when the number of clock pulses after Chip Select

( S ) being driven Low is an exact multiple of eight.

All attempts to access the memory array during a Write Status

Register cycle, Program cycle or Erase cycle are ignored, and

the internal Write Status Register cycle, Program cycle or

Erase cycle continues unaffected.

Table 3. Instruction Set

Instruction

Description

One-byte

Instruction Code

Address

Bytes

WREN

Write Enable

0000 0110 06h

0

WRDI

Write Disable

0000 0100 04h

0

RDSR

Read Status Register

0000 0101 05h

0

WRSR

Write Status Register

0000 0001 01h

0

READ

Read Data Bytes

0000 0011 03h

3

FAST_READ

Read Data Bytes at Higher Speed

0000 1011 0Bh

3

FAST_READ_DUAL Read Data Bytes at Higher Speed by

_OUTPUT

Dual Output (1)

00111011

3Bh

3

FAST_READ_DUAL Read Data Bytes at Higher Speed by

_INPUT-OUTPUT

Dual Input and Dual Output (1)

10111011

BBh

3(2)

PP

Page Program

0000 0010 02h

3

SE

Sector Erase

0010 0000 20h

3

BE

Block Erase

1101 1000 D8h

3

CE

Chip Erase

1100 0111 C7h

0

DP

Deep Power-down

1011 1001 B9h

0

RDID

Read Device Identification

1001 1111 9Fh

0

REMS

Read Electronic Manufacturer & Device

Identification

1001 0000

90h

1(3)

RES

Release from Deep Power-down, and

Read Electronic Signature

1010 1011 ABh

0

Release from Deep Power-down

0

Note: (1) DIO = (D6, D4, D2, D0)

DO = (D7, D5, D3, D1)

(2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0)

DO = (A23, A21, A19, …….., A7, A5, A3, A1)

(3) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first

Dummy

Bytes

0

0

0

0

0

1

1

1(2)

0

0

0

0

0

0

2

3

0

Data

Bytes

0

0

1 to ∞

1

1 to ∞

1 to ∞

1 to ∞

1 to ∞

1 to 256

0

0

0

0

1 to ∞

1 to ∞

1 to ∞

0

(April, 2008, Version 0.0)

10

AMIC Technology Corp.

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