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89C1051U

8-Bit Microcontroller with 1K Bytes Flash

Atmel Corporation 

AT89C1051U

Restrictions on Certain Instructions

The AT89C1051U and is an economical and cost-effective

member of Atmel’s growing family of microcontrollers. It

contains 1K bytes of flash program memory. It is fully com-

patible with the MCS-51 architecture, and can be pro-

grammed using the MCS-51 instruction set. However, there

are a few considerations one must keep in mind when uti-

lizing certain instructions to program this device.

All the instructions related to jumping or branching should

be restricted such that the destination address falls within

the physical program memory space of the device, which is

1K for the AT89C1051U. This should be the responsibility

of the software programmer. For example, LJMP 3FEH

would be a valid instruction for the AT89C1051U (with 1K

of memory), whereas LJMP 410H would not.

1. Branching instructions:

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR

These unconditional branching instructions will execute

correctly as long as the programmer keeps in mind that the

destination branching address must fall within the physical

boundaries of the program memory size (locations 00H to

3FFH for the 89C1051U). Violating the physical space lim-

its may cause unknown program behavior.

CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With

these conditional branching instructions the same rule

above applies. Again, violating the memory boundaries

may cause erratic execution.

For applications involving interrupts the normal interrupt

service routine address locations of the 80C51 family archi-

tecture have been preserved.

2. MOVX-related instructions, Data Memory:

The AT89C1051U contains 64 bytes of internal data mem-

ory. Thus, in the AT89C1051U the stack depth is limited to

64 bytes, the amount of available RAM. External DATA

memory access is not supported in this device, nor is exter-

nal PROGRAM memory execution. Therefore, no MOVX

[...] instructions should be included in the program.

A typical 80C51 assembler will still assemble instructions,

even if they are written in violation of the restrictions men-

tioned above. It is the responsibility of the controller user to

know the physical features and limitations of the device

being used and adjust the instructions used correspond-

ingly.

Programmable Serial UART Channel(1)

The AT89C1051U offers a programmable serial port which

is compatible with the serial ports on other AT89 series

flash MCU products. A detailed description of the serial port

operation can be found in the Hardware Description section

of the Atmel AT89 series flash MCU data book.

Note: 1. This feature is not available on the AT89C1051.

Program Memory Lock Bits

On the chip are two lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the table below:

Lock Bit Protection Modes(1)

Program Lock Bits

LB1 LB2 Protection Type

1

U

U No program lock features.

2

P

U Further programming of the Flash

is disabled.

3

P

P Same as mode 2, also verify is

disabled.

Note: 1. The Lock Bits can only be erased with the Chip Erase

operation.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

P1.0 and P1.1 should be set to ’0’ if no external pullups are

used, or set to ’1’ if external pullups are used.

It should be noted that when idle is terminated by a hard-

ware reset, the device normally resumes program execu-

tion, from where it left off, up to two machine cycles before

the internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when Idle is terminated by

reset, the instruction following the one that invokes Idle

should not be one that writes to a port pin or to external

memory.

Power Down Mode

In the power down mode the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardware reset.

Reset redefines the SFRs but does not change the on-chip

RAM. The reset should not be activated before VCC is

restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and sta-

bilize.

P1.0 and P1.1 should be set to ’0’ if no external pullups are

used, or set to ’1’ if external pullups are used.

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