87C552 Ver la hoja de datos (PDF) - Philips Electronics
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Fabricante
87C552
Philips Electronics
87C552 Datasheet PDF : 24 Pages
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Philips Semiconductors
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Product specification
87C552
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC PLCC
QFP TYPE
NAME AND FUNCTION
ALE/PROG
48
49
O Address Latch Enable: Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG)
during EPROM programming.
EA/VPP
49
50
I External Access: When EA is held at TTL level high, the CPU executes out of the internal
program ROM provided the program counter is less than 8192. When EA is held at TTL
low level, the CPU executes out of external program memory. EA is not allowed to float.
This pin also receives the 12.75V programming supply voltage (VPP) during EPROM
programming.
AVREF–
58
59
I Analog to Digital Conversion Reference Resistor: Low-end.
AVREF+
59
60
I Analog to Digital Conversion Reference Resistor: High-end.
AVSS
60
61
I Analog Ground
AVDD
61
63
I Analog Power Supply
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5V or VSS – 0.5V,
respectively.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
IDLE MODE
In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VDD and RST must come up at the same time for a proper start-up.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.
Table 1. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM
MEMORY
ALE
PSEN
PORT 0 PORT 1
Idle
Internal
1
1
Data
Data
Idle
External
1
1
Float
Data
Power-down
Internal
0
0
Data
Data
Power-down
External
0
0
Float
Data
PORT 2
Data
Address
Data
Data
PORT 3
Data
Data
Data
Data
PORT 4
Data
Data
Data
Data
PWM0/
PWM1
High
High
High
High
1998 May 01
6
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