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Gigabit Ethernet Controller

Intel 

82575 Gigabit Ethernet Controller Datasheet

1.0

1.1

1.2

Introduction

The Intel® 82575 Gigabit Ethernet Controller is a single, compact component with two

fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY)

ports. The device uses the PCI Express Base Specification, Rev.1.1RD.

The Intel 82575 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX, and 10BASE-T applications (802.3z, 802.3u, and 802.3ab). Ports also

contain a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber)

and Gigabit backplane applications. In addition to managing MAC and PHY Ethernet

layer functions, the controller manages PCI Express packet traffic across its

transaction, link, and physical/logical layers. The SERDES can be used in SGMII mode

to connect to external PHY, either on-board or via the SFP connector.

The Intel 82575’s on-board System Management Bus (SMB) ports enable network

manageability implementations required by information technology personnel for

remote control and alerting via the LAN. With SMB, management packets can be routed

to or from a management processor. Enhanced pass-through capabilities also allow

system remote control over standardized interfaces. Also included is a new

manageability interface, NC-SI that supports the DMTF preOS sideband protocol. An

internal management interface called MDIO enables the MAC (and software) to monitor

and control the PHY. Both ports support the Wake on LAN feature.

The 82575 Gigabit Ethernet Controller with PCI Express architecture is designed for

high performance and low memory latency. The device is optimized to connect to a

system Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the

82575 controller can connect to an I/O Control Hub that has a PCI Express interface.

Wide internal data paths eliminate performance bottlenecks by efficiently handling

large address and data words. Combining a parallel and pipe-lined logic architecture

optimized for Gigabit Ethernet and independent transmit and receive queues, the

82575 controller efficiently handles packets with minimum latency. The 82575

controller includes advanced interrupt handling features, including MSI-X support. The

82575 uses efficient ring buffer descriptor data structures, with up to 64 packet

descriptors cached on chip. A large 48 KByte per port on-chip packet buffer maintains

superior performance. In addition, using hardware acceleration, the controller offloads

tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation.

The 82575 operation can be configured using EEPROM and FLASH; it can be also be

used in EEPROM-less configurations.

The 82575 is packaged in a 25mm X 25mm, 576-pin flip chip ball grid array (FCBGA).

Document Scope

This document contains targeted datasheet specifications for the 82575 Gigabit

Ethernet Controller, including signal descriptions, DC and AC parameters, packaging

data, and pinout information.

Reference Documents

This application assumes that the designer is acquainted with high-speed design and

board layout techniques. The following documents provide additional information:

82575 Gigabit Ethernet Controller Design Guide. Intel Corporation.

Intel Ethernet Controllers Timing Device Selection Guide. Intel Corporation.

PCI Express Base Specification, Revision 1.1.

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