82443ZX Ver la hoja de datos (PDF) - Intel

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82443ZX

Intel® 440ZX AGPset: 82443ZX Host Bridge/Controller

Intel 

Architectural Overview

Figure 1-1. Intel® 440ZX AGPset System Block Diagram

Pentium® II

Processor

Video

- DVD

- Camera

- VCR

- VMI

- Video Capture

Host Bus

Graphics

Device

2X AGP Bus

82443ZX

Host Bridge

66/100

MHz

Main

Memory

Display

Encoder

TV

Video BIOS

Graphics

Local Memory

3.3V EDO &

SDRAM Support

PCI Slots

Primary PCI Bus

(PCI Bus #0)

2 IDE Ports

(Ultra DMA/33)

2 USB USB

Ports USB

System BIOS

82371EB

(PIIX4E)

(PCI-to-ISA

Bridge)

System MGMT (SM) Bus

ISA Slots

ISA Bus

sys_blk.vsd

Host Interface

The Pentium II processor supports a second level cache via a back-side bus (BSB) interface. All

control for the L2 cache is handled by the processor. The 82443ZX provides bus control signals

and address paths for transfers between the processors front-side bus (host bus), PCI bus, AGP and

main memory. The 82443ZX supports a 4-deep in-order queue (i.e., supports pipelining of up to 4

outstanding transaction requests on the host bus). Due to the system concurrency requirements,

along with support for pipelining of address requests from the host bus, the 82443ZX supports

request queuing for all three interfaces (Host, AGP and PCI).

Host-initiated I/O cycles are decoded to PCI, AGP or PCI configuration space. Host-initiated

memory cycles are decoded to PCI, AGP (prefetchable or non-prefetchable memory space) or

DRAM (including AGP aperture memory). For memory cycles (host, PCI or AGP initiated) that

target the AGP aperture space in DRAM, the 82443ZX translates the address using the AGP

address translation table. Other host cycles forwarded to AGP are defined by the AGP address

map.

1-2

82443ZX Host Bridge Datasheet

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