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M5LV-256/74-5YI

MACH 5 CPLD Family Fifth Generation MACH Architecture

Lattice Semiconductor 

Advanced power management options allow designers to incrementally reduce power while

maintaining the level of performance needed for today’s complex designs. I/O safety features

allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system

programmable through an IEEE 1149.1 Test Access Port (TAP) interface.

FUNCTIONAL DESCRIPTION

The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block

interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the

block interconnect is called a segment. The second level of interconnect, the segment

interconnect, ties all of the segments together. The only logic difference between any two MACH

5 devices is the number of segments. Therefore, once a designer is familiar with one device,

consistent performance can be expected across the entire family. All devices have four clock pins

available which can also be used as logic inputs.

CLK

Block:

16 MCs

4

Segment:

4 Blocks

Segment Interconnect

Figure 1. MACH 5 Block Diagram

20446G-001

The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block

resembles an independent PAL device, it has superior control and logic generation capabilities.

x I/O cells

x Product-term array and Logic Allocator

x Macrocells

x Register control generator

x Output enable generator

I/O Cells

The I/Os associated with each PAL block have a path directly back to that PAL block called local

feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect

line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment

interconnects provide connections between any two signals in a device. The block feeder assigns

block interconnect lines and local feedback lines to the PAL block inputs.

4

MACH 5 Family

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