GM72V66841CT-7K Ver la hoja de datos (PDF) - LG

Número de pieza

componentes Descripción

Fabricante

GM72V66841CT-7K

2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM

LG 

LG Semicon

CKE Truth Table

GM72V66841CT/CLT

Current

State

Active

Function

Clock suspend

mode entry

CKE

n -1 n CS RAS CAS WE Address

HL H X X X

X

Any

Clock suspend

LL X X X X

X

Clock Suspend

Clock suspend

mode exit

LH X X X X

X

Idle

Auto-refresh

command

(REF)

HH

L

L

L

H

X

Idle

Self-refresh

entry

(SELF) H L

L

L

L

H

X

Idle

Self refresh

Power down

Power down

entry

Self refresh

exit

Power down

Exit

HL L H H H

X

HL H X X X

X

(SELFX) L H L

HHH

X

LH H X X X

X

LH L H H H

X

LH H X X X

X

* Notes : H: VIH, L: VIL, X: VIH or VIL.

Clock suspend mode entry: The synchronous

DRAM enters Clock suspend mode from active

mode by setting CKE to Low. The Clock suspend

mode changes depending on the current status (1

Clock before) as shown below.

ACTIVE Clock suspend: This suspend mode

ignores inputs after the next Clock by internally

maintaining the bank active status.

READ suspend and READ A suspend: The

data being output is held (and continues to be

output).

WRITE suspend and WRIT A suspend: In

this mode, external signals are not accepted.

However, the internal state is held.

Clock suspend: During Clock suspend mode,

keep the CKE to Low.

Clock suspend mode exit : The synchronous

DRAM exits from Clock suspend mode by

setting CKE to High during the Clock suspend

state.

IDLE: In this state, all banks are not selected,

and completed Precharge operation.

7

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