74LVX573TTR(2004) Ver la hoja de datos (PDF) - STMicroelectronics

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74LVX573TTR
(Rev.:2004)

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS

STMicroelectronics 

74LVX573

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH

(3-STATE NON INV.) WITH 5V TOLERANT INPUTS

s HIGH SPEED:

tPD=6.4ns (TYP.) at VCC = 3.3V

s 5V TOLERANT INPUTS

s POWER-DOWN PROTECTION ON INPUTS

s INPUT VOLTAGE LEVEL:

) VIL = 0.8V, VIH = 2V at VCC =3V

t(s s LOW POWER DISSIPATION:

c ICC = 4 µA (MAX.) at TA=25°C

u s LOW NOISE:

d VOLP = 0.3V (TYP.) at VCC =3.3V

ro s SYMMETRICAL OUTPUT IMPEDANCE:

P |IOH| = IOL = 4 mA (MIN) at VCC = 3V

s BALANCED PROPAGATION DELAYS:

te tPLH ≅ tPHL

le s OPERATING VOLTAGE RANGE:

o VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

bs s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

- O s IMPROVED LATCH-UP IMMUNITY

t(s) DESCRIPTION

The 74LVX573 is a low voltage CMOS OCTAL

c D-TYPE LATCH with 3 STATE OUTPUT NON

du INVERTING fabricated with sub-micron silicon

ro gate and double-layer metal wiring C2MOS

technology. It is ideal for low power, battery

P operated and low noise 3.3V applications.

te This 8 bit D-Type latch is controlled by a latch

le enable input (LE) and an output enable input (OE).

o While the LE input is held at a high level, the Q

s outputs will follow the data input precisely.

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74LVX573MTR

74LVX573TTR

When the LE is taken low, the Q outputs will be

latched precisely at the logic level of D input data.

While the (OE) input is low, the 8 outputs will be in

a normal logic state (high or low logic level) and

while high level the outputs will be in a high

impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V. It

combines high speed performance with the true

CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Ob Figure 1: Pin Connection And IEC Logic Symbols

August 2004

Rev. 4

1/13

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