74LVX125MT Ver la hoja de datos (PDF) - Fairchild Semiconductor
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74LVX125MT Datasheet PDF : 6 Pages
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February 1994
Revised February 2005
74LVX125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVX125 contains four independent non-inverting buff-
ers with 3-STATE outputs. The inputs tolerate voltages up
to 7V allowing the interface of 5V systems to 3V systems.
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
Package
Number
Package Description
74LVX125M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX125SJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX125MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX125MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 1)
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
An
OEn
On
Description
Inputs
Output Enable Inputs
Outputs
Truth Table
Inputs
OEn
An
L
L
L
H
H
X
H HIGH Voltage Level
L LOW Voltage Level
Z High Impedance
X Immaterial
Output
On
L
H
Z
© 2005 Fairchild Semiconductor Corporation DS012007
www.fairchildsemi.com
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