NXP Semiconductors
74LVC1G14
Single Schmitt-trigger inverter
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd = fi × (tr × ∆ICC(AV) + tf × ∆ICC(AV)) × VCC where:
Padd = additional power dissipation (µW);
fi = input frequency (MHz);
tr = input rise time (ns); 10 % to 90 %;
tf = input fall time (ns); 90 % to 10 %;
∆ICC(AV) = average additional supply current (µA).
Average ∆ICC(AV) differs with positive or negative input transitions, as shown in Figure 12.
An example of a relaxation circuit using the 74LVC1G14 is shown in Figure 13.
12
average
I CC
(mA) 10
8
mna642
positive-going
edge
6
4
negative-going
2
edge
0
0
2
4
6
VCC (V)
Linear change of VI between 0.8 V to 2.0 V.
All values given are typical unless otherwise specified.
Fig 12. Average additional supply current as a function of supply voltage
R
f = T-1-- ≈ 0---.--5----×-1----R----C---
Fig 13. Relaxation oscillator
C
mna035
74LVC1G14_7
Product data sheet
Rev. 07 — 18 July 2007
© NXP B.V. 2007. All rights reserved.
9 of 16