74LVC1G125 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVC1G125 Datasheet PDF : 20 Pages
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74LVC1G125
Bus buffer/line driver; 3-state
Rev. 11 — 2 July 2012
Product data sheet
1. General description
The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (OE). A HIGH-level at pin OE
causes the output to assume a high-impedance OFF-state.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
24 mA output drive (VCC = 3.0 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CMOS low power consumption
Inputs accept voltages up to 5 V
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
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