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74LV4020D Datasheet PDF : 20 Pages
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Philips Semiconductors
74LV4020
14-stage binary ripple counter
Table 8: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9.
Symbol Parameter
Conditions
Min Typ Max Unit
tW
pulse width
CP (HIGH and LOW)
see Figure 7
MR (HIGH)
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 8
41
-
-
ns
30
-
-
ns
24
-
-
ns
18
-
-
ns
trec
recovery time
MR to CP
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 8
41
-
-
ns
30
-
-
ns
24
-
-
ns
18
-
-
ns
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
fmax
maximum input clock frequency see Figure 7
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
ns
26
-
-
ns
19
-
-
ns
15
-
-
ns
12
-
-
ns
12
-
-
MHz
16
-
-
MHz
20
-
-
MHz
30
-
-
MHz
[1] Typical values are measured at nominal VCC and Tamb = 25 °C.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74LV4020_1
Product data sheet
Rev. 01 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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