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74LV139PWDH

Dual 2-to-4 line decoder/demultiplexer

Philips Electronics 

Philips Semiconductors

Dual 2-to-4 line decoder/demultiplexer

Product specification

74LV139

FEATURES

• Wide operating voltage: 1.0 to 5.5 V

• Optimized for low voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,

Tamb = 25°C

• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,

Tamb = 25°C

• Demultiplexing capability

• Two independent 2-to-4 decoders

• Multifunction capability

• Active LOW mutually exclusive outputs

• Output capability: standard

• ICC category: MSI

APPLICATIONS

• Memory decoding or data-routing

• Code conversion

DESCRIPTION

The 74LV139 is a low-voltage Si-gate CMOS device that is pin and

function compatible with 74HC/HCT139.

The 74LV139 is a dual 2-to-4 line decoder/demultiplexer. This device

has two independent decoders, each accepting two binary weighted

inputs (nA0 and nA1) and providing four mutually exclusive active

LOW outputs (nY0 to nY3). Each decoder has an active LOW enable

input (nE).

When nE is HIGH, every output is forced HIGH. The enable can be

used as the data input for a 1-to-4 demultiplexer application.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

Propagation delay

nAn to nYn,

nE to nYn

CL = 15 pF;

VCC = 3.3 V

CI

Input capacitance

CPD

Power dissipation capacitance per

multiplexer

VCC = 3.3 V

VI = GND to VCC1

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

ȍ (CL × VCC2 × fo) = sum of the outputs.

TYPICAL

11

10

3.5

42

ORDERING INFORMATION

PACKAGES

16-Pin Plastic DIL

16-Pin Plastic SO

16-Pin Plastic SSOP Type II

16-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

–40°C to +125°C

–40°C to +125°C

–40°C to +125°C

–40°C to +125°C

OUTSIDE NORTH AMERICA

74LV139 N

74LV139 D

74LV139 DB

74LV139 PW

NORTH AMERICA

74LV139 N

74LV139 D

74LV139 DB

74LV139PW DH

UNIT

ns

pF

pF

PKG. DWG. #

SOT38-4

SOT109-1

SOT338-1

SOT403-1

PIN CONFIGURATION

1E 1

1A0 2

1A1 3

1Y0 4

1Y1 5

1Y2 6

1Y3 7

GND 8

16 VCC

15 2E

14 2A0

13 2A1

9 2Y0

10 2Y1

11 2Y2

12 2Y3

SV00530

PIN DESCRIPTION

PIN

NUMBER

SYMBOL

FUNCTION

1, 15

1E, 2E Enable inputs (active LOW)

2, 3

4, 5, 6, 7

8

1A0, 1A1

1Y0 to 1Y3

GND

Address inputs

Outputs (active LOW)

Ground (0 V)

12, 11, 10, 9

14, 13

16

2Y0 to 2Y3

2A0, 2A1

VCC

Outputs (active LOW)

Address inputs

Positive supply voltage

1998 Apr 28

2

853–1922 19290

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