74LV109N Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
74LV109N Datasheet PDF : 12 Pages
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Philips Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger
Product specification
74LV109
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
nJ, nK
INPUT
GND
VI
nCP
INPUT
GND
VOH
nQ
OUTPUT
VOL
VOH
nQ
OUTPUT
VOL
VM
t su
th
1/f max
VM
tW
t PHL
VM
VM
t PLH
t su
th
t PLH
t PHL
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00522
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK to nCP set-up, the nCP to
nJ, nK hold times and the maximum clock pulse frequency.
TEST CIRCUIT
VCC
PULSE
GENERATOR
VI
RT
D.U.T.
VO
50pF
CL
RL = 1k
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST
tPLH/tPHL
VCC
< 2.7V
2.7–3.6V
VI
VCC
2.7V
SV00901
Figure 3. Load circuitry for switching times.
Vl
nCP
INPUT
GND
Vl
nSD
INPUT
GND
Vl
nRD
INPUT
GND
VOH
nQ
OUTPUT
VOL
VOH
nQ
OUTPUT
VOL
VM
tW
tPLH
VM
tPHL
VM
VM
trem
trem
tW
VM
tPHL
tPLH
SV00523
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths and the nRD,
nSD to nCP removal time.
1998 Apr 20
7
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