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74LV109N

Dual JK flip-flop with set and reset; positive-edge trigger

Philips Electronics 

Philips Semiconductors

Dual JK flip-flop with set and reset; positive-edge trigger

Product specification

74LV109

FEATURES

• Optimized for low voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,

Tamb = 25°C

• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,

Tamb = 25°C

• Output capability: standard

• ICC category: flip-flops

DESCRIPTION

The 74LV109 is a low-voltage Si-gate CMOS device that is pin and

function compatible with 74HC/HCT109.

The 74LV109 is a dual positive-edge triggered JK-type flip-flop

featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset

(RD) inputs; also complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate

independently of the clock input.

The J and K inputs control the state changes of the flip-flops as

described in the mode select function table. The J and K inputs must

be stable one set-up time prior to the LOW-to-HIGH clock transition

for predictable operation.

The JK design allows operation as a D-type flip-flop by tying the

J and K inputs together.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns

SYMBOL

PARAMETER

Schmitt-trigger action in the clock input makes the circuit highly

tolerant to slower clock rise and fall times.

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

Propagation delay

nCP to nQ, nQ

nSD to nQ, nQ

nRD to nQ, nQ

CL = 15 pF;

VCC = 3.3 V

fmax

Maximum clock frequency

CI

Input capacitance

CPD

Power dissipation capacitance per flip-flop VI = GND to VCC1

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

Σ (CL × VCC2 × fo) = sum of the outputs.

14

12

ns

12

77

MHz

3.5

pF

20

pF

ORDERING INFORMATION

PACKAGES

16-Pin Plastic DIL

16-Pin Plastic SO

16-Pin Plastic SSOP Type II

16-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

–40°C to +125°C

–40°C to +125°C

–40°C to +125°C

–40°C to +125°C

OUTSIDE NORTH AMERICA

74LV109 N

74LV109 D

74LV109 DB

74LV109 PW

NORTH AMERICA

74LV109 N

74LV109 D

74LV109 DB

74LV109PW DH

PKG. DWG. #

SOT38-4

SOT109-1

SOT338-1

SOT403-1

PIN CONFIGURATION

1RD 1

1J 2

1K 3

1CP 4

1S D 5

1Q 6

1Q 7

GND 8

16 VCC

15 2R D

14 2J

13 2K

12 2CP

11 2SD

10 2Q

9 2Q

SV00517

PIN DESCRIPTION

PIN

NUMBER

SYMBOL

FUNCTION

1, 15

1RD, 2RD

Asynchronous reset input

(active LOW)

2, 14, 3, 13

1J, 2J,

1K, 2K

Synchronous inputs; flip-flops 1 and 2

4, 12

1CP, 2CP

Clock input (LOW-to-HIGH,

edge-triggered)

5, 11

1SD, 2SD

Asynchronous set inputs

(active LOW)

6, 10

1Q, 2Q True flip-flop outputs

7, 9

1Q, 2Q Complement flip-flop outputs

8

GND

Ground (0 V)

16

VCC

Positive supply voltage

1998 Apr 20

2

853-1986 19255

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