74F379(1999) Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
74F379 Datasheet PDF : 6 Pages
| |||
Unit Loading/Fan Out
Pin Names
E
D0–D3
CP
Q0–Q3
Q0–Q3
Description
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
Complement Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
Truth Table
The 74F379 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock (CP) and Enable (E) inputs are common to all flip-
flops. When the E is input HIGH, the register will retain the
present data independent of the CP input. The Dn and E
inputs can change when the clock is in either state, pro-
vided that the recommended setup and hold times are
observed.
Inputs
E
H
CP
Dn
X
L
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
NC = No Change
Outputs
Qn
Qn
NC
NC
H
L
L
H
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Share Link: 