74F373 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
74F373 Datasheet PDF : 8 Pages
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Unit Loading/Fan Out
Pin Names
Description
D0–D7
LE
OE
O0–O7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-STATE Latch Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Functional Description
Truth Table
The 74F373 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
Inputs
data on the Dn inputs enters the latches. In this condition
LE
OE
Dn
the latches are transparent, i.e., a latch output will change
H
L
H
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
H
L
L
inputs a setup time preceding the HIGH-to-LOW transition
L
L
X
of LE. The 3-STATE buffers are controlled by the Output
X
H
X
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
H = HIGH Voltage Level
L = LOW Voltage Level
impedance mode but this does not interfere with entering X = Immaterial
new data into the latches.
Z = High Impedance State
Output
On
H
L
On (no change)
Z
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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